diff options
Diffstat (limited to 'src/southbridge/amd/sb700')
| -rw-r--r-- | src/southbridge/amd/sb700/bootblock.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 20 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/fadt.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sata.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sm.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/usb.c | 2 |
8 files changed, 23 insertions, 23 deletions
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 012a22cd58..222b33df72 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -44,7 +44,7 @@ static void sb700_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5); - if (IS_ENABLED(CONFIG_SPI_FLASH)) + if (CONFIG(SPI_FLASH)) /* Disable decode of variable LPC ROM address ranges 1 and 2. */ reg8 &= ~((1 << 3) | (1 << 4)); else @@ -100,7 +100,7 @@ static void sb700_configure_rom(void) dev = PCI_DEV(0, 0x14, 3); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { + if (CONFIG(SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { uint32_t prev_spi_cfg; volatile uint32_t *spi_mmio; diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index af2b6c1bce..3b801bafe8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -151,7 +151,7 @@ void sb7xx_51xx_lpc_init(void) reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -165,7 +165,7 @@ void sb7xx_51xx_lpc_init(void) // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -404,7 +404,7 @@ static void sb700_devices_por_init(void) printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__); } else { - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { + if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { /* Disable legacy sensor support / reset ASF Slave state machine per RPR 2.27 step 3 */ outb(0x40, SMBUS_AUX_IO_BASE + SMBSLVMISC); } @@ -459,7 +459,7 @@ static void sb700_devices_por_init(void) /*pci_write_config8(dev, 0x79, 0x4F); */ pci_write_config8(dev, 0x78, 0xFF); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { printk(BIOS_DEBUG, "%s: Disabling ISA DMA support\n", __func__); /* Disable LPC ISA DMA Capability */ byte = pci_read_config8(dev, 0x78); @@ -484,7 +484,7 @@ static void sb700_devices_por_init(void) /* LPC Device, BDF:0-20-3 */ printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); } @@ -531,7 +531,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); if (!sata_ahci_mode){ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0); @@ -597,7 +597,7 @@ static void sb700_pmio_por_init(void) uint8_t enable_c_states; enable_c_states = 0; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) if (get_option(&byte, "cpu_c_states") == CB_SUCCESS) enable_c_states = !!byte; #endif @@ -608,7 +608,7 @@ static void sb700_pmio_por_init(void) byte |= 0x20; pmio_write(0x66, byte); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { + if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { /* RPR 2.11 Sx State Settings */ byte = pmio_read(0x65); byte &= ~(1 << 7); /* SpecialFunc = 0 */ @@ -687,7 +687,7 @@ static void sb700_pmio_por_init(void) byte |= 0xc0; pmio_write(0xbb, byte); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* RPR 2.26 Alter CPU reset timing */ byte = pmio_read(0xb2); byte |= 0x1 << 2; /* Enable CPU reset timing option */ @@ -736,7 +736,7 @@ static void sb700_pci_cfg(void) * mentioned in RPR. But I keep them. The registers and the * comments are compatible. */ dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* Enabling LPC DMA function. */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index 94fc5dc4a1..4bc36221ad 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -155,7 +155,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) amd_powernow_update_fadt(fadt); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 2ebd7a59ce..eae8f04e49 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -45,13 +45,13 @@ static void lpc_init(struct device *dev) pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) +#if CONFIG(SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n"); #else isa_dma_init(); #endif - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); @@ -66,7 +66,7 @@ static void lpc_init(struct device *dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ @@ -246,7 +246,7 @@ static void sb700_lpc_enable_resources(struct device *dev) sb700_lpc_enable_childrens_resources(dev); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); @@ -275,7 +275,7 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 98b8b6ad77..39aef639d2 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -351,7 +351,7 @@ static void sata_init(struct device *dev) byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 8929f3fdfc..e3594fd583 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -222,7 +222,7 @@ void sb7xx_51xx_enable(struct device *dev) } } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 4c3992d8d5..6b7ce68a1a 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -136,7 +136,7 @@ static void sm_init(struct device *dev) pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ else byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ @@ -305,7 +305,7 @@ static void sm_init(struct device *dev) pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } byte = pci_read_config8(dev, 0xAE); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + if (CONFIG(ENABLE_APIC_EXT_ID)) byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 9805bf6bc1..da653112d7 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -181,7 +181,7 @@ static void usb_init2(struct device *dev) dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 Erratum 36 */ dword &= ~(1 << 26); if (!ehci_async_data_cache) |