diff options
Diffstat (limited to 'src/southbridge/amd/sb600/stage1_reset.c')
| -rw-r--r-- | src/southbridge/amd/sb600/stage1_reset.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/src/southbridge/amd/sb600/stage1_reset.c b/src/southbridge/amd/sb600/stage1_reset.c deleted file mode 100644 index cc069e5a44..0000000000 --- a/src/southbridge/amd/sb600/stage1_reset.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/pci.h> -#include <msr.h> -#include <legacy.h> -#include <device/pci_ids.h> -#include <statictree.h> -#include <config.h> - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only resets coherent link table, but - * does not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} |