diff options
Diffstat (limited to 'src/southbridge/amd/rs780')
| -rw-r--r-- | src/southbridge/amd/rs780/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/early_setup.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 16 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/pcie.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.h | 6 |
5 files changed, 19 insertions, 19 deletions
diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h index 5c64a1a8f5..7a893c783f 100644 --- a/src/southbridge/amd/rs780/chip.h +++ b/src/southbridge/amd/rs780/chip.h @@ -31,7 +31,7 @@ struct southbridge_amd_rs780_config u8 gfx_lane_reversal; /* Single/Dual slot lan reversal */ u8 gfx_tmds; /* whether support TMDS? */ u8 gfx_compliance; /* whether support compliance? */ - u8 gfx_reconfiguration; /* Dynamic Lind Width Control */ + u8 gfx_reconfiguration; /* Dynamic Link Width Control */ u8 gfx_link_width; /* Desired width of lane 2 */ u8 gfx_pcie_config; /* GFX PCIE Modes */ u8 gfx_ddi_config; /* GFX DDI Modes */ diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index a36112bebb..d35ecddf14 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -256,17 +256,17 @@ static void rs780_htinit(void) set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); /* Enables error-retry mode */ set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1); - /* Enables scrambling and Disalbes command throttling */ + /* Enables scrambling and Disables command throttling */ set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); /* Enables transmitter de-emphasis */ set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31); - /* Enabels transmitter de-emphasis level */ + /* Enables transmitter de-emphasis level */ /* Sets training 0 time */ set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14); /* Enables strict TM4 detection */ set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22); - /* Enables proprer DLL reset sequence */ + /* Enables proper DLL reset sequence */ set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10); /* HyperTransport 3 Processor register settings to be done in northbridge */ diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 2825925534..30a5c69a10 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -19,7 +19,7 @@ /* * for rs780 internal graphics device - * device id of internal grphics: + * device id of internal graphics: * RS780: 0x9610 * RS780C: 0x9611 * RS780M: 0x9612 @@ -355,7 +355,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200}; static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800}; - /* We definetely will use this in future. Just leave it here. */ + /* We definitely will use this in future. Just leave it here. */ /*struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)dev->chip_info;*/ @@ -961,7 +961,7 @@ static void rs780_internal_gfx_enable(device_t dev) set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044); set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00); #if 0 - /* Controller Termation. */ + /* Controller Termination. */ set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000); #endif @@ -1124,8 +1124,8 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) if (!result) { /* Powers down all lanes for port A */ /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */ - /* Note: I have to disable the slot where there isnt a device, - * otherwise the system will hang. I dont know why. */ + /* Note: I have to disable the slot where there isn't a device, + * otherwise the system will hang. I don't know why. */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind); } else { /* step 16.b Link Training was successful */ @@ -1423,7 +1423,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* done by enable_pci_bar3() before */ /* step 7 compliance state, (only need if CMOS option is enabled) */ - /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */ + /* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */ if (cfg->gfx_compliance) { /* force compliance */ set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6); @@ -1452,7 +1452,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.6. Disables RC ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9); - /* Enabels TLP flushing. */ + /* Enables TLP flushing. */ /* Note: It is got from RS690. The system will hang without this action. */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); @@ -1530,7 +1530,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) 1 << 0 | 0x1F << 1 | 0x1F << 6, 1 << 0 | 0x04 << 1 | 0x04 << 6); - /* Single-port/Dual-port configureation. */ + /* Single-port/Dual-port configuration. */ switch (cfg->gfx_dual_slot) { case 0: /* step 1, lane reversal (only need if build config option is enabled) */ diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index fcf3d9427a..060838ca9c 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -149,12 +149,12 @@ static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev) reg &= ~(1 << 31); nbmisc_write_index(nb_dev, 0x66, reg); - /* 5.5.7.5-6. read bit14 and write back its inverst value */ + /* 5.5.7.5-6. read bit14 and write back its inverted value */ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); reg ^= RECONFIG_GPPSB_GPPSB; nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); #else - /* 5.5.7.5-6. read bit14 and write back its inverst value */ + /* 5.5.7.5-6. read bit14 and write back its inverted value */ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); reg ^= RECONFIG_GPPSB_GPPSB; nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); @@ -300,7 +300,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16); /* 5.10.8.22. Disable GEN2 */ - /* TODO: should be 2 seperated cases. */ + /* TODO: should be 2 separated cases. */ set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31); set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5); set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31); @@ -351,7 +351,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) case 10: /* 5.10.8.5. Blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - /* Enabels TLP flushing */ + /* Enables TLP flushing */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* check port enable */ diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index c44a81347b..f84604df58 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -78,7 +78,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ULONG ulSystemConfig; //[0]=1: PowerExpress mode // =0 Non-PowerExpress mode; -//[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will disable other power state in VBIOS table. +//[1]=1: system boots up at AMD overdriven state or user customized mode. In this case, driver will disable other power state in VBIOS table. // =0: system boots up at driver control state. Power state depends on VBIOS PP table. //[2]=1: PWM method is used on NB voltage control. // =0: GPIO method is used. @@ -90,7 +90,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 // =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. //[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored. // =0: Voltage settings is determined by VBIOS PP table. -//[7]=1: Enable CLMC Hybird Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. +//[7]=1: Enable CLMC Hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. // =0: Enable regular CLMC mode, CDLD and CILR will be enabled. //[8]=1: CDLF is supported and enabled by fuse //CHP 914 // =0: CDLF is not supported and not enabled by fuses @@ -174,7 +174,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 * ------------------------------------------------- */ extern PCIE_CFG AtiPcieCfg; -/* ----------------- export funtions ----------------- */ +/* ----------------- export functions ----------------- */ u32 nbmisc_read_index(device_t nb_dev, u32 index); void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); u32 nbpcie_p_read_index(device_t dev, u32 index); |