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Diffstat (limited to 'src/southbridge/amd/rs690/pcie.c')
-rw-r--r--src/southbridge/amd/rs690/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index 043c2eef5c..db65686a11 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* step 6d: ASPM L1 for the southbridge link */
/* To enable L1s in the southbridge*/
- /* step 6e: ASPM L1 for GPP link(s) */;
+ /* step 6e: ASPM L1 for GPP link(s) */
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);