aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/amd/pi/hudson
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/amd/pi/hudson')
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/fch.asl8
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/usb.asl8
-rw-r--r--src/southbridge/amd/pi/hudson/amd_pci_int_defs.h6
-rw-r--r--src/southbridge/amd/pi/hudson/amd_pci_int_types.h6
-rw-r--r--src/southbridge/amd/pi/hudson/early_setup.c2
-rw-r--r--src/southbridge/amd/pi/hudson/fadt.c4
-rw-r--r--src/southbridge/amd/pi/hudson/gpio.h4
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.c6
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h2
-rw-r--r--src/southbridge/amd/pi/hudson/lpc.c4
-rw-r--r--src/southbridge/amd/pi/hudson/pci_devs.h4
-rw-r--r--src/southbridge/amd/pi/hudson/sata.c2
12 files changed, 28 insertions, 28 deletions
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 17f5140a71..4e1e7d1856 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -47,7 +47,7 @@ Device(SBUS) {
#include "usb.asl"
/* 0:14.2 - HD Audio */
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if !CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#include "audio.asl"
#endif
@@ -129,7 +129,7 @@ Method(_CRS, 0) {
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#if CONFIG(HUDSON_IMC_FWM)
/* TODO: It is unstable.
* might be fixed by restructuring
*/
@@ -161,8 +161,8 @@ Method(_INI, 0) {
/* Determine the OS we're running on */
OSFL()
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
+#if CONFIG(HUDSON_IMC_FWM)
+#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
ITZE() /* enable IMC Fan Control*/
#endif
#endif
diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl
index e36c661990..423c48a42a 100644
--- a/src/southbridge/amd/pi/hudson/acpi/usb.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl
@@ -50,8 +50,8 @@ Device(UOH6) {
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
- !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
+ !CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
@@ -65,8 +65,8 @@ Device(XHC0) {
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
- !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
+ !CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
index 1b5326b88e..448b85e72b 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
@@ -63,12 +63,12 @@
#define PIRQ_IDE 0x40 /* IDE 14h.1 */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON)
#define FCH_INT_TABLE_SIZE 0x63
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#endif
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define FCH_INT_TABLE_SIZE 0x54
#define PIRQ_GPP0 0x50 /* GPP INT 0 */
#define PIRQ_GPP1 0x51 /* GPP INT 1 */
@@ -76,7 +76,7 @@
#define PIRQ_GPP3 0x53 /* GPP INT 3 */
#endif
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#define FCH_INT_TABLE_SIZE 0x76
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#define PIRQ_I2C0 0x70
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index 8061bf7349..fc7a5d1cfd 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -23,13 +23,13 @@ const char *intr_types[] = {
[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
[0x7F] = "RSVD\t",
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON)
[0x40] = "RSVD\t", "SATA\t",
[0x60] = "RSVD\t", "RSVD\t", "GPIO\t",
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#elif CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
[0x62] = "GPIO\t",
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 25be669750..abfa897752 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -27,7 +27,7 @@
#include "pci_devs.h"
#include <Fch/Fch.h>
-#if IS_ENABLED(CONFIG_HUDSON_UART)
+#if CONFIG(HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index 075c577e5e..28e20d38ca 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -27,7 +27,7 @@
#include "hudson.h"
#include "smi.h"
-#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)
+#if CONFIG(HUDSON_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
@@ -63,7 +63,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;
fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;
diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h
index dad2279e6c..f07855d765 100644
--- a/src/southbridge/amd/pi/hudson/gpio.h
+++ b/src/southbridge/amd/pi/hudson/gpio.h
@@ -25,7 +25,7 @@
#define GPIO_OUTPUT_VALUE (1 << 22)
#define GPIO_OUTPUT_ENABLE (1 << 23)
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* GPIO_0 - GPIO_62 */
#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500)
#define GPIO_0 (GPIO_BANK0_CONTROL + 0x00)
@@ -124,7 +124,7 @@
#define GPIO_146 (GPIO_BANK2_CONTROL + 0x48)
#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C)
#define GPIO_148 (GPIO_BANK2_CONTROL + 0x50)
-#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */
+#endif /* CONFIG(SOUTHBRIDGE_AMD_PI_KERN) */
typedef uint32_t gpio_t;
diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c
index 4db03d8abe..e1ea2ce4b3 100644
--- a/src/southbridge/amd/pi/hudson/hudson.c
+++ b/src/southbridge/amd/pi/hudson/hudson.c
@@ -99,7 +99,7 @@ static void hudson_init_acpi_ports(void)
/* CpuControl is in \_PR.CP00, 6 bytes */
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);
hudson_enable_acpi_cmd_smi();
} else {
@@ -119,9 +119,9 @@ static void hudson_init(void *chip_info)
static void hudson_final(void *chip_info)
{
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
agesawrapper_fchecfancontrolservice();
- if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
+ if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
enable_imc_thermal_zone();
}
}
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 27ae4edf47..6afcc651e2 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -191,7 +191,7 @@ void lpc_wideio_16_window(uint16_t base);
void hudson_tpm_decode_spi(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#if IS_ENABLED(CONFIG_HUDSON_UART)
+#if CONFIG(HUDSON_UART)
void configure_hudson_uart(void);
#endif
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index 1d504ae598..abb92f29d2 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -86,7 +86,7 @@ static void lpc_init(struct device *dev)
/* Set up SERIRQ, enable continuous mode */
byte = (BIT(4) | BIT(7));
- if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
+ if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
byte |= BIT(6);
pm_write8(PM_SERIRQ_CONF, byte);
@@ -353,7 +353,7 @@ static struct device_operations lpc_ops = {
.read_resources = hudson_lpc_read_resources,
.set_resources = hudson_lpc_set_resources,
.enable_resources = hudson_lpc_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h
index 7d4dea2938..579dfaede2 100644
--- a/src/southbridge/amd/pi/hudson/pci_devs.h
+++ b/src/southbridge/amd/pi/hudson/pci_devs.h
@@ -71,7 +71,7 @@
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define IDE_DEV 0x14
#define IDE_FUNC 1
#define IDE_DEVID 0x780C
@@ -104,7 +104,7 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define SB_PCIE_DEV 0x15
#define SB_PCIE_PORT1_FUNC 0
#define SB_PCIE_PORT2_FUNC 1
diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c
index 4268bc2f34..153fe6dea4 100644
--- a/src/southbridge/amd/pi/hudson/sata.c
+++ b/src/southbridge/amd/pi/hudson/sata.c
@@ -23,7 +23,7 @@
static void sata_init(struct device *dev)
{
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/**************************************
* Configure the SATA port multiplier *
**************************************/
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 19:28:30 +0000