diff options
Diffstat (limited to 'src/southbridge/amd/cs5530')
| -rw-r--r-- | src/southbridge/amd/cs5530/cs5530.h | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5530/cs5530_enable_rom.c | 47 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5530/cs5530_isa.c | 8 |
3 files changed, 53 insertions, 8 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530.h b/src/southbridge/amd/cs5530/cs5530.h index df4f66bae0..107b6f26e5 100644 --- a/src/southbridge/amd/cs5530/cs5530.h +++ b/src/southbridge/amd/cs5530/cs5530.h @@ -27,6 +27,12 @@ void cs5530_enable(device_t dev); #endif #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ +#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ + +#define LOWER_ROM_ADDRESS_RANGE (1 << 0) +#define ROM_WRITE_ENABLE (1 << 1) +#define UPPER_ROM_ADDRESS_RANGE (1 << 2) +#define BIOS_ROM_POSITIVE_DECODE (1 << 5) /* Selects PCI positive decoding for accesses to the configured ROM space. */ #define BIOS_ROM_POSITIVE_DECODE (1 << 5) diff --git a/src/southbridge/amd/cs5530/cs5530_enable_rom.c b/src/southbridge/amd/cs5530/cs5530_enable_rom.c new file mode 100644 index 0000000000..09ec3ed791 --- /dev/null +++ b/src/southbridge/amd/cs5530/cs5530_enable_rom.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "cs5530.h" + +static void cs5530_enable_rom(void) +{ + uint8_t reg8; + + /* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */ + device_t dev = PCI_DEV(0, 0x12, 0); + + /* + * Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and + * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. + * + * Make the ROM write-protected. + */ + reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG); + reg8 |= LOWER_ROM_ADDRESS_RANGE; + reg8 |= UPPER_ROM_ADDRESS_RANGE; + reg8 &= ~ROM_WRITE_ENABLE; + pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); + + /* Set positive decode on ROM. */ + reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2); + reg8 |= BIOS_ROM_POSITIVE_DECODE; + pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); +} diff --git a/src/southbridge/amd/cs5530/cs5530_isa.c b/src/southbridge/amd/cs5530/cs5530_isa.c index a4d3b2eadb..ad41bd20cd 100644 --- a/src/southbridge/amd/cs5530/cs5530_isa.c +++ b/src/southbridge/amd/cs5530/cs5530_isa.c @@ -45,14 +45,6 @@ static void cs5530_read_resources(device_t dev) static void isa_init(struct device *dev) { - uint8_t reg8; - - // TODO: Test if needed, otherwise drop. - - /* Set positive decode on ROM. */ - reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2); - reg8 |= BIOS_ROM_POSITIVE_DECODE; - pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); } static void cs5530_pci_dev_enable_resources(device_t dev) |