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Diffstat (limited to 'src/southbridge/amd/common')
-rw-r--r--src/southbridge/amd/common/amd_pci_util.c3
-rw-r--r--src/southbridge/amd/common/amd_pci_util.h3
2 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index f10a459bfd..b6d6308710 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -22,8 +22,6 @@
#include "amd_pci_int_defs.h"
#include "amd_pci_int_types.h"
-#ifndef __PRE_RAM__
-
const struct pirq_struct * pirq_data_ptr = NULL;
u32 pirq_data_size = 0;
const u8 *intr_data_ptr = NULL;
@@ -195,4 +193,3 @@ void write_pci_cfg_irqs(void)
} /* for (dev = all_devices) */
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
-#endif /* __PRE_RAM__ */
diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h
index 9a4695e29a..0a3ce23a84 100644
--- a/src/southbridge/amd/common/amd_pci_util.h
+++ b/src/southbridge/amd/common/amd_pci_util.h
@@ -23,8 +23,6 @@
#define PCI_INTR_INDEX 0xc00
#define PCI_INTR_DATA 0xc01
-#ifndef __PRE_RAM__
-
struct pirq_struct {
u8 devfn;
u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */
@@ -39,6 +37,5 @@ u8 read_pci_int_idx(u8 index, int mode);
void write_pci_int_idx(u8 index, int mode, u8 data);
void write_pci_cfg_irqs(void);
void write_pci_int_table (void);
-#endif /* __PRE_RAM */
#endif /* AMD_PCI_UTIL_H */