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-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/pcie.asl4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
index 65ac920efa..f69ba1db24 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
@@ -29,9 +29,7 @@ Scope(\) {
}
Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space