diff options
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/acpi/fch.asl')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/acpi/fch.asl | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index a3a17a4f35..59b556b5b0 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -7,23 +7,23 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) + Return (0) } Method(_STA, 0) { /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ + Return (0x0b) /* Status is visible */ } Method(_PRT,0) { @@ -126,12 +126,12 @@ Method(_CRS, 0) { * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ /* @@ -160,8 +160,8 @@ Method(_INI, 0) { OSFL() /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + /*if (\SBRI <= 0x13) { + * \PWDE = 0 * } */ } /* End Method(_SB._INI) */ @@ -173,10 +173,10 @@ Scope(\){ CMTI, 8, /* Client Management Data register */ G64E, 1, - G64O, 1, - G32O, 2, + G64O, 1, + G32O, 2, , 2, - GPSL, 2, + GPSL, 2, } /* GPM Port register */ |