diff options
Diffstat (limited to 'src/southbridge/amd/agesa')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/chip.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.c | 30 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/sd.c | 69 |
4 files changed, 102 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 7802600c4e..44e030cf9a 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -8,6 +8,8 @@ ramstage-y += sata.c ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c +ramstage-y += sd.c + ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index d54a3962b2..d5f14ff683 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -28,6 +28,7 @@ struct southbridge_amd_agesa_hudson_config u32 boot_switch_sata_ide : 1; u32 hda_viddid; u8 gpp_configuration; + u8 sd_mode; #endif }; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 84013d1d62..e4cbc07342 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -100,6 +100,36 @@ u8 pm2_ioread(u8 reg) void hudson_enable(device_t dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); + switch (dev->path.pci.devfn) { + case (0x14 << 3) | 7: /* 0:14.7 SD */ + if (dev->enabled == 0) { + // read the VENDEV ID + device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); + u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16; + /* turn off the SDHC controller in the PM reg */ + u8 sd_tmp; + if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) { + outb(0xE7, PM_INDEX); + sd_tmp = inb(PM_DATA); + sd_tmp &= ~(1 << 0); + outb(sd_tmp, PM_DATA); + } + else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) { + outb(0xE8, PM_INDEX); + sd_tmp = inb(PM_DATA); + sd_tmp &= ~(1 << 0); + outb(sd_tmp, PM_DATA); + } + /* remove device 0:14.7 from PCI space */ + outb(0xD3, PM_INDEX); + sd_tmp = inb(PM_DATA); + sd_tmp &= ~(1 << 6); + outb(sd_tmp, PM_DATA); + } + break; + default: + break; + } } struct cbmem_entry *get_cbmem_toc(void) diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c new file mode 100644 index 0000000000..941bb97d27 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "hudson.h" + +static void sd_init(struct device *dev) +{ + u32 stepping; + + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); + + struct southbridge_amd_agesa_hudson_config *sd_chip = + (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); + + if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + pci_write_config32(dev, 0xA4, 0x31FEC8B2); + pci_write_config32(dev, 0xA8, 0x00002503); + pci_write_config32(dev, 0xB0, 0x02180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + else { /* SD 2.0 mode */ + if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ + pci_write_config32(dev, 0xA4, 0x31DE32B2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000058B); + } + else { /* Stepping >= A1 */ + pci_write_config32(dev, 0xA4, 0x31FE3FB2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + } +} + +static struct device_operations sd_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .scan_bus = 0, +}; + +static const struct pci_driver sd_driver __pci_driver = { + .ops = &sd_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_YANGTZE_SD, +}; |