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-rw-r--r--src/southbridge/amd/agesa/hudson/acpi/fch.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
index 38f2bca6da..b87b9e4946 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
@@ -67,7 +67,7 @@ Name(CRES, ResourceTemplate() {
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
+ * PCI buses can have 256 secondary buses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/