diff options
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/imc.c')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/imc.c | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 1d63c1e36a..934d1e95da 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -14,6 +14,7 @@ */ #include "imc.h" +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <Porting.h> #include <AGESA.h> @@ -22,24 +23,22 @@ #include <Proc/Fch/Common/FchCommonCfg.h> #include <Proc/Fch/FchPlatform.h> -#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - void imc_reg_init(void) { /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); + pm2_write8(0, 0x06); + pm2_write8(1, 0x06); + pm2_write8(2, 0xf7); + pm2_write8(3, 0xff); + pm2_write8(4, 0xff); #if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); + pm2_write8(0x10, 0x06); + pm2_write8(0x11, 0x06); + pm2_write8(0x12, 0xf7); + pm2_write8(0x13, 0xff); + pm2_write8(0x14, 0xff); #endif #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |