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-rw-r--r--src/soc/mediatek/common/include/soc/dramc_param_common.h73
-rw-r--r--src/soc/mediatek/mt8186/include/soc/dramc_param.h71
-rw-r--r--src/soc/mediatek/mt8192/include/soc/dramc_param.h60
-rw-r--r--src/soc/mediatek/mt8195/include/soc/dramc_param.h60
4 files changed, 73 insertions, 191 deletions
diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h
index 1b68d61d09..09b89cbe62 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param_common.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h
@@ -8,6 +8,21 @@
* file should be synced to the other repository.
*/
+#include <soc/dramc_soc.h>
+
+enum DRAMC_PARAM_STATUS_CODES {
+ DRAMC_SUCCESS = 0,
+ DRAMC_ERR_INVALID_VERSION,
+ DRAMC_ERR_INVALID_SIZE,
+ DRAMC_ERR_INVALID_FLAGS,
+ DRAMC_ERR_RECALIBRATE,
+ DRAMC_ERR_INIT_DRAM,
+ DRAMC_ERR_COMPLEX_RW_MEM_TEST,
+ DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST,
+ DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST,
+ DRAMC_ERR_FAST_CALIBRATION,
+};
+
enum DRAMC_PARAM_FLAG {
DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
};
@@ -26,4 +41,62 @@ struct dramc_param_header {
u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */
};
+enum SDRAM_DDR_TYPE {
+ DDR_TYPE_DISCRETE,
+ DDR_TYPE_EMCP,
+};
+
+enum SDRAM_DDR_GEOMETRY_TYPE {
+ DDR_TYPE_2CH_2RK_4GB_2_2,
+ DDR_TYPE_2CH_2RK_6GB_3_3,
+ DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
+ DDR_TYPE_2CH_1RK_4GB_4_0,
+ DDR_TYPE_2CH_2RK_6GB_2_4,
+ DDR_TYPE_2CH_2RK_8GB_4_4,
+};
+
+struct sdram_info {
+ u32 ddr_type; /* SDRAM_DDR_TYPE */
+ u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */
+};
+
+struct emi_mdl {
+ u32 cona_val;
+ u32 conh_val;
+ u32 conf_val;
+ u32 chn_cona_val;
+};
+
+struct ddr_mrr_info {
+ u16 mr5_vendor_id;
+ u16 mr6_revision_id;
+ u16 mr7_revision_id;
+ u64 mr8_density[RANK_MAX];
+ u32 rank_nums;
+ u8 die_num[RANK_MAX];
+};
+
+enum SDRAM_DVFS_FLAG {
+ DRAMC_DISABLE_DVFS,
+ DRAMC_ENABLE_DVFS,
+};
+
+enum SDRAM_VOLTAGE_TYPE {
+ SDRAM_VOLTAGE_NVCORE_NVDRAM,
+ SDRAM_VOLTAGE_HVCORE_HVDRAM,
+ SDRAM_VOLTAGE_LVCORE_LVDRAM,
+};
+
+struct ddr_base_info {
+ u32 config_dvfs; /* SDRAM_DVFS_FLAG */
+ struct sdram_info sdram;
+ u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
+ u32 support_ranks;
+ u64 rank_size[RANK_MAX];
+ struct emi_mdl emi_config;
+ DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
+ struct ddr_mrr_info mrr_info;
+ u32 data_rate;
+};
+
#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
index b5c019fbff..2d6212b169 100644
--- a/src/soc/mediatek/mt8186/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
@@ -15,49 +15,6 @@
#define DRAMC_PARAM_HEADER_VERSION 1
-enum DRAMC_PARAM_STATUS_CODES {
- DRAMC_SUCCESS = 0,
- DRAMC_ERR_INVALID_VERSION,
- DRAMC_ERR_INVALID_SIZE,
- DRAMC_ERR_INVALID_FLAGS,
- DRAMC_ERR_RECALIBRATE,
- DRAMC_ERR_INIT_DRAM,
- DRAMC_ERR_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_FAST_CALIBRATION,
-};
-
-enum SDRAM_DVFS_FLAG {
- DRAMC_DISABLE_DVFS,
- DRAMC_ENABLE_DVFS,
-};
-
-enum SDRAM_DDR_TYPE {
- DDR_TYPE_DISCRETE,
- DDR_TYPE_EMCP,
-};
-
-enum SDRAM_DDR_GEOMETRY_TYPE {
- DDR_TYPE_2CH_2RK_4GB_2_2,
- DDR_TYPE_2CH_2RK_6GB_3_3,
- DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
- DDR_TYPE_2CH_1RK_4GB_4_0,
- DDR_TYPE_2CH_2RK_6GB_2_4,
- DDR_TYPE_2CH_2RK_8GB_4_4,
-};
-
-enum SDRAM_VOLTAGE_TYPE {
- SDRAM_VOLTAGE_NVCORE_NVDRAM,
- SDRAM_VOLTAGE_HVCORE_HVDRAM,
- SDRAM_VOLTAGE_LVCORE_LVDRAM,
-};
-
-struct sdram_info {
- u32 ddr_type; /* SDRAM_DDR_TYPE */
- u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */
-};
-
struct sdram_params {
/* Sometimes, we may need to compare params member
* between coreboot and blob for analysis. Here,
@@ -110,34 +67,6 @@ struct sdram_params {
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
};
-struct emi_mdl {
- u32 cona_val;
- u32 conh_val;
- u32 conf_val;
- u32 chn_cona_val;
-};
-
-struct ddr_mrr_info {
- u16 mr5_vendor_id;
- u16 mr6_revision_id;
- u16 mr7_revision_id;
- u64 mr8_density[RANK_MAX];
- u32 rank_nums;
- u8 die_num[RANK_MAX];
-};
-
-struct ddr_base_info {
- u32 config_dvfs; /* SDRAM_DVFS_FLAG */
- struct sdram_info sdram;
- u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
- u32 support_ranks;
- u64 rank_size[RANK_MAX];
- struct emi_mdl emi_config;
- DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
- struct ddr_mrr_info mrr_info;
- u32 data_rate;
-};
-
struct dramc_data {
struct ddr_base_info ddr_info;
struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
index 09501b0ca5..a5357c9cd2 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
@@ -15,49 +15,6 @@
#define DRAMC_PARAM_HEADER_VERSION 7
-enum DRAMC_PARAM_STATUS_CODES {
- DRAMC_SUCCESS = 0,
- DRAMC_ERR_INVALID_VERSION,
- DRAMC_ERR_INVALID_SIZE,
- DRAMC_ERR_INVALID_FLAGS,
- DRAMC_ERR_RECALIBRATE,
- DRAMC_ERR_INIT_DRAM,
- DRAMC_ERR_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_FAST_CALIBRATION,
-};
-
-enum SDRAM_DVFS_FLAG {
- DRAMC_DISABLE_DVFS,
- DRAMC_ENABLE_DVFS,
-};
-
-enum SDRAM_DDR_TYPE {
- DDR_TYPE_DISCRETE,
- DDR_TYPE_EMCP,
-};
-
-enum SDRAM_DDR_GEOMETRY_TYPE {
- DDR_TYPE_2CH_2RK_4GB_2_2,
- DDR_TYPE_2CH_2RK_6GB_3_3,
- DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
- DDR_TYPE_2CH_1RK_4GB_4_0,
- DDR_TYPE_2CH_2RK_6GB_2_4,
- DDR_TYPE_2CH_2RK_8GB_4_4,
-};
-
-enum SDRAM_VOLTAGE_TYPE {
- SDRAM_VOLTAGE_NVCORE_NVDRAM,
- SDRAM_VOLTAGE_HVCORE_HVDRAM,
- SDRAM_VOLTAGE_LVCORE_LVDRAM,
-};
-
-struct sdram_info {
- u32 ddr_type; /* SDRAM_DDR_TYPE */
- u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */
-};
-
struct sdram_params {
u32 rank_num;
u16 num_dlycell_perT;
@@ -105,23 +62,6 @@ struct sdram_params {
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
};
-struct emi_mdl {
- u32 cona_val;
- u32 conh_val;
- u32 conf_val;
- u32 chn_cona_val;
-};
-
-struct ddr_base_info {
- u32 config_dvfs; /* SDRAM_DVFS_FLAG */
- struct sdram_info sdram;
- u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
- u32 support_ranks;
- u64 rank_size[RANK_MAX];
- struct emi_mdl emi_config;
- DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
-};
-
struct dramc_data {
struct ddr_base_info ddr_info;
struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
index bfa5f8d2e6..11efbe1475 100644
--- a/src/soc/mediatek/mt8195/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
@@ -15,49 +15,6 @@
#define DRAMC_PARAM_HEADER_VERSION 8
-enum DRAMC_PARAM_STATUS_CODES {
- DRAMC_SUCCESS = 0,
- DRAMC_ERR_INVALID_VERSION,
- DRAMC_ERR_INVALID_SIZE,
- DRAMC_ERR_INVALID_FLAGS,
- DRAMC_ERR_RECALIBRATE,
- DRAMC_ERR_INIT_DRAM,
- DRAMC_ERR_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST,
- DRAMC_ERR_FAST_CALIBRATION,
-};
-
-enum SDRAM_DVFS_FLAG {
- DRAMC_DISABLE_DVFS,
- DRAMC_ENABLE_DVFS,
-};
-
-enum SDRAM_DDR_TYPE {
- DDR_TYPE_DISCRETE,
- DDR_TYPE_EMCP,
-};
-
-enum SDRAM_DDR_GEOMETRY_TYPE {
- DDR_TYPE_2CH_2RK_4GB_2_2,
- DDR_TYPE_2CH_2RK_6GB_3_3,
- DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
- DDR_TYPE_2CH_1RK_4GB_4_0,
- DDR_TYPE_2CH_2RK_6GB_2_4,
- DDR_TYPE_2CH_2RK_8GB_4_4,
-};
-
-enum SDRAM_VOLTAGE_TYPE {
- SDRAM_VOLTAGE_NVCORE_NVDRAM,
- SDRAM_VOLTAGE_HVCORE_HVDRAM,
- SDRAM_VOLTAGE_LVCORE_LVDRAM,
-};
-
-struct sdram_info {
- u32 ddr_type; /* SDRAM_DDR_TYPE */
- u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */
-};
-
struct sdram_params {
u32 rank_num;
u16 num_dlycell_perT;
@@ -105,23 +62,6 @@ struct sdram_params {
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
};
-struct emi_mdl {
- u32 cona_val;
- u32 conh_val;
- u32 conf_val;
- u32 chn_cona_val;
-};
-
-struct ddr_base_info {
- u32 config_dvfs; /* SDRAM_DVFS_FLAG */
- struct sdram_info sdram;
- u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
- u32 support_ranks;
- u64 rank_size[RANK_MAX];
- struct emi_mdl emi_config;
- DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
-};
-
struct dramc_data {
struct ddr_base_info ddr_info;
struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 13:43:34 +0000