diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/bootblock/pch.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/bootblock/pch.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 9 |
7 files changed, 48 insertions, 13 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index b7d2c15d3c..bc921e3a4a 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -65,11 +65,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 242aa71141..8ebfb3dcf3 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -77,11 +77,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 9224c486ec..e1b7d85c5a 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -62,11 +62,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index f36bd31e3b..a6b6b20e67 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -58,11 +58,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index f59d9c909f..96a7dc2b32 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -62,11 +62,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c6b2ad966a..38ae916dad 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -29,9 +29,14 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 18ca5e51af..5c4d1d5fb7 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -67,11 +67,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. |