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-rw-r--r--src/soc/intel/alderlake/include/soc/meminit.h7
-rw-r--r--src/soc/intel/alderlake/meminit.c5
2 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index ae86cc6da4..9813d9345e 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -20,11 +20,10 @@ struct mem_ddr_config {
/* Dqs Pins Interleaved Setting. Enable/Disable Control */
bool dq_pins_interleaved;
/*
- * Rcomp resistor values. These values represent the resistance in
- * ohms of the three rcomp resistors attached to the DDR_COMP_0,
- * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ * Rcomp resistor value. This values represents the resistance in
+ * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
*/
- uint16_t rcomp_resistor[3];
+ uint16_t rcomp_resistor;
/* Rcomp target values. */
uint16_t rcomp_targets[5];
};
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 5b65ef063f..dcff61113a 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -28,9 +28,8 @@ static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp
static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)
{
mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved;
- memcpy(&mem_cfg->RcompResistor, ddr_config->rcomp_resistor,
- sizeof(mem_cfg->RcompResistor));
- memcpy(&mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
+ mem_cfg->RcompResistor = ddr_config->rcomp_resistor;
+ memcpy(mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
}
static const struct soc_mem_cfg soc_mem_cfg[] = {