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-rw-r--r--src/soc/intel/tigerlake/fsp_params_jsl.c11
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c10
2 files changed, 15 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c
index 8eb3fbacaf..6cb3b6718d 100644
--- a/src/soc/intel/tigerlake/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/fsp_params_jsl.c
@@ -158,9 +158,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
- if (!dev || !xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 0587b88868..9e22b58e7c 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -115,9 +115,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;