diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/i2c.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock.c | 8 |
4 files changed, 17 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index cdb871b916..fdacb9f525 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -15,10 +15,10 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL }, - { PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL }, - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), }; static void reset_i2c_peripherals(void) diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 4a7a7e83a0..22a408ec92 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -35,6 +35,13 @@ struct soc_i2c_scl_pin { uint8_t pin_mask; }; +/* Macro to populate the elements of the array of soc_i2c_scl_pin in the SoC code */ +#define I2C_RESET_SCL_PIN(pin_name, pin_mask_value) \ +{ \ + .pin = PAD_CFG_STRUCT(pin_name, pin_name ## _IOMUX_GPIOxx, PAD_OUTPUT(HIGH)), \ + .pin_mask = pin_mask_value, \ +} + /** * Information about I2C peripherals that need to be reset. * @i2c_scl_reset_mask: Bit mask of I2C buses that need to be reset based on the device tree diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 048ce12819..ae3aed2d98 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -17,8 +17,8 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), /* I2C4 is a peripheral device only */ }; diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 499ff633d4..8c6fde521a 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -30,10 +30,10 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL }, - { PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL }, - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), }; /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ |