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-rw-r--r--src/soc/amd/cezanne/cpu.c24
-rw-r--r--src/soc/amd/common/block/cpu/noncar/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/cpu/noncar/mpinit.c26
-rw-r--r--src/soc/amd/glinda/cpu.c25
-rw-r--r--src/soc/amd/mendocino/cpu.c25
-rw-r--r--src/soc/amd/phoenix/cpu.c25
-rw-r--r--src/soc/amd/picasso/cpu.c25
7 files changed, 27 insertions, 124 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index c1cf663336..2c3100fc81 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,39 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-}
-
static void zen_2_3_init(struct device *dev)
{
check_mca();
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index 27510bf540..3204667fc1 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -10,5 +10,6 @@ romstage-y += memmap.c
ramstage-y += cpu.c
romstage-y += cpu.c
ramstage-y += memmap.c
+ramstage-y += mpinit.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/mpinit.c b/src/soc/amd/common/block/cpu/noncar/mpinit.c
new file mode 100644
index 0000000000..002c50537f
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/mpinit.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <amdblocks/iomap.h>
+#include <console/console.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <device/device.h>
+#include <types.h>
+
+void mp_init_cpus(struct bus *cpu_bus)
+{
+ extern const struct mp_ops amd_mp_ops_with_smm;
+ if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
+ "mp_init_with_smm failed. Halting.\n");
+
+ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+ mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
+ FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
+
+ /* SMMINFO only needs to be set up when booting from S5 */
+ if (!acpi_is_wakeup_s3())
+ apm_control(APM_CNT_SMMINFO);
+}
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index f780f2193d..91f6a9f248 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -2,41 +2,16 @@
/* TODO: Update for Glinda */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
-#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-}
-
static void zen_2_3_init(struct device *dev)
{
check_mca();
diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c
index 5d6bb169d7..842b04fb25 100644
--- a/src/soc/amd/mendocino/cpu.c
+++ b/src/soc/amd/mendocino/cpu.c
@@ -1,40 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
-#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-}
-
static void zen_2_3_init(struct device *dev)
{
check_mca();
diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c
index 19327776d9..05dac9a032 100644
--- a/src/soc/amd/phoenix/cpu.c
+++ b/src/soc/amd/phoenix/cpu.c
@@ -2,41 +2,16 @@
/* TODO: Update for Phoenix */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
-#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-}
-
static void zen_2_3_init(struct device *dev)
{
check_mca();
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index be767dcd18..4f846293a8 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -1,40 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization. */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-
-}
-
static void model_17_init(struct device *dev)
{
check_mca();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 07:39:29 +0000