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-rw-r--r--src/soc/intel/skylake/include/soc/gpio.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index ae534cd9ce..4f809cf480 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -140,6 +140,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
PAD_FIELD(HOSTSW, GPIO))
+/* General purpose input passed through to GPIO interrupt */
+#define PAD_CFG_GPI_INT(pad_, term_, rst_, trig_) \
+ _PAD_CFG_ATTRS(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, trig_, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
+ PAD_FIELD(HOSTSW, GPIO))
+
/* General purpose input passed through to IOxAPIC. Assume APIC logic can
* handle polarity/edge/level constraints. */
#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \