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-rw-r--r--src/soc/intel/broadwell/chip.h10
-rw-r--r--src/soc/intel/broadwell/gma.c13
2 files changed, 12 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 81c9780776..b77cb71f70 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -19,11 +19,11 @@ struct soc_intel_broadwell_config {
u8 gpu_dp_d_hotplug;
/* Panel power sequence timings */
- u8 gpu_panel_power_cycle_delay;
- u16 gpu_panel_power_up_delay;
- u16 gpu_panel_power_down_delay;
- u16 gpu_panel_power_backlight_on_delay;
- u16 gpu_panel_power_backlight_off_delay;
+ u16 gpu_panel_power_cycle_delay_ms;
+ u16 gpu_panel_power_up_delay_ms;
+ u16 gpu_panel_power_down_delay_ms;
+ u16 gpu_panel_power_backlight_on_delay_ms;
+ u16 gpu_panel_power_backlight_off_delay_ms;
/* Panel backlight settings */
unsigned int gpu_pch_backlight_pwm_hz;
diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c
index c033b499f5..9866ed3b39 100644
--- a/src/soc/intel/broadwell/gma.c
+++ b/src/soc/intel/broadwell/gma.c
@@ -4,6 +4,7 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <bootmode.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
@@ -298,24 +299,24 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
- reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
+ reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32);
}
/* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) {
- reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
+ reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32);
}
/* Setup Panel Power Cycle Delay */
- if (conf->gpu_panel_power_cycle_delay) {
+ if (conf->gpu_panel_power_cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f;
- reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
+ reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}