diff options
Diffstat (limited to 'src/soc')
28 files changed, 32 insertions, 32 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 9261d54f87..c1cf663336 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -22,7 +22,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index b38ce80895..372f51517b 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -48,7 +48,7 @@ before_carstage: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index e123c361cc..72d778886a 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -63,6 +63,6 @@ bootblock_pre_c_entry: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index a6d9a739f4..b81b9bcd1d 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -20,7 +20,7 @@ static void soc_finalize(void *unused) acpi_enable_sci(); } - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index 49cd11cdbf..f780f2193d 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -25,7 +25,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c index c742db0e75..5d6bb169d7 100644 --- a/src/soc/amd/mendocino/cpu.c +++ b/src/soc/amd/mendocino/cpu.c @@ -23,7 +23,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c index 2c8f77130a..19327776d9 100644 --- a/src/soc/amd/phoenix/cpu.c +++ b/src/soc/amd/phoenix/cpu.c @@ -25,7 +25,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c0b918e5c0..be767dcd18 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -22,7 +22,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 3aedd0eb88..f2df3cecde 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -24,7 +24,7 @@ void mp_init_cpus(struct bus *cpu_bus) { extern const struct mp_ops amd_mp_ops_with_smm; if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 2900045a66..460c8af174 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -91,7 +91,7 @@ static void soc_finalize(void *unused) heci_finalize(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 79614afc16..b64364bed8 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -146,7 +146,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) } else if (s3resume) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); + post_code(POSTCODE_RESUME_FAILURE); system_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 20bb18736d..d71ac0996d 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -58,7 +58,7 @@ static void broadwell_finalize(void *unused) broadwell_pch_finalize(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index d088e5145c..c55e755055 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -102,7 +102,7 @@ static void sdram_initialize(struct pei_data *pei_data) /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); + post_code(POSTCODE_RESUME_FAILURE); system_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 9df4ac35b9..837f1573f8 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -84,7 +84,7 @@ static void soc_config_acpibase(void) pmc_base_reg = get_pmc_reg_base(); if (!pmc_base_reg) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Invalid PMC base address\n"); pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index e45ae9ae98..ba7fc69b55 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -93,7 +93,7 @@ static void soc_finalize(void *unused) heci1_disable(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 6a19792bf4..8afb6ff517 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -18,7 +18,7 @@ External(\_SB.PCI0.LPCB.EC0.WAK, MethodObj) Method (_PTS, 1) { - DBG0 = POST_OS_ENTER_PTS + DBG0 = POSTCODE_OS_ENTER_PTS If (CondRefOf (\_SB.PCI0.LPCB.EC0.PTS)) { @@ -42,7 +42,7 @@ Method (_PTS, 1) Method (_WAK, 1) { - DBG0 = POST_OS_ENTER_WAKE + DBG0 = POSTCODE_OS_ENTER_WAKE If (CondRefOf (\_SB.PCI0.LPCB.EC0.WAK)) { diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f2ae72c38a..5f6b6de07c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -302,7 +302,7 @@ before_carstage: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 0126a122f6..7532c7d707 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -20,7 +20,7 @@ bootblock_pre_c_entry: .global cache_as_ram cache_as_ram: - post_code(POST_BOOTBLOCK_CAR) + post_code(POSTCODE_BOOTBLOCK_CAR) movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx @@ -99,7 +99,7 @@ CAR_init_done: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 81a5d342f0..f163e229a9 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -117,7 +117,7 @@ uintptr_t graphics_get_framebuffer_address(void) memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2); if (!memory_base) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Graphic memory bar2 is not programmed!"); memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET; @@ -140,7 +140,7 @@ static uintptr_t graphics_get_gtt_base(void) if (!gtt_base) { gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0); if (!gtt_base) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "GTTMMADR is not programmed!"); } return gtt_base; diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c index 537f388cb2..70fbcaa147 100644 --- a/src/soc/intel/common/block/p2sb/p2sblib.c +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -50,7 +50,7 @@ void p2sb_dev_unhide(pci_devfn_t dev) p2sb_dev_set_hide_bit(dev, 0); if (p2sb_dev_is_hidden(dev)) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Unable to unhide the P2SB device!\n"); } @@ -59,7 +59,7 @@ void p2sb_dev_hide(pci_devfn_t dev) p2sb_dev_set_hide_bit(dev, 1); if (!p2sb_dev_is_hidden(dev)) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Unable to hide the P2SB device!\n"); } diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 37d857978c..2805011a78 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -62,7 +62,7 @@ static void pch_pmc_read_resources(struct device *dev) struct pmc_resource_config *config = &pmc_cfg; if (pmc_soc_get_resources(config) < 0) - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Unable to get PMC controller resource information!"); /* Get the normal PCI resources of this device. */ diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index d6ab737de4..275413b4ef 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -49,7 +49,7 @@ static void soc_finalize(void *unused) heci_finalize(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 5665d75340..6cff7a80f3 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -78,7 +78,7 @@ static void soc_finalize(void *unused) apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index d249dd4489..c2b1819f64 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -238,7 +238,7 @@ static void soc_init_final_device(void *chip_info) fsp_handle_reset(reset_status); /* Control shouldn't return here */ - die_with_post_code(POST_HW_INIT_FAILURE, + die_with_post_code(POSTCODE_HW_INIT_FAILURE, "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); } diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 6bd304cea6..a977b0516e 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -83,7 +83,7 @@ static void soc_finalize(void *unused) heci_finalize(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index afa1c02f4d..fd80aeac1a 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -109,7 +109,7 @@ static void soc_finalize(void *unused) apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 283efb50df..cd02745a9e 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -61,7 +61,7 @@ static void soc_finalize(void *unused) heci1_disable(); /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index 7830a4b27f..af630fe812 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -70,7 +70,7 @@ static void soc_finalize(void *unused) lock_msr_ppin_ctl(NULL); } - post_code(POST_OS_BOOT); + post_code(POSTCODE_OS_BOOT); } static void bios_done_finalize(void *unused) |