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-rw-r--r--src/soc/intel/broadwell/adsp.c4
-rw-r--r--src/soc/intel/broadwell/chip.h72
-rw-r--r--src/soc/intel/broadwell/include/soc/ramstage.h1
-rw-r--r--src/soc/intel/broadwell/lpc.c8
-rw-r--r--src/soc/intel/broadwell/me.c4
-rw-r--r--src/soc/intel/broadwell/pch.c13
-rw-r--r--src/soc/intel/broadwell/pch/chip.h78
-rw-r--r--src/soc/intel/broadwell/pcie.c6
-rw-r--r--src/soc/intel/broadwell/romstage/pch.c6
-rw-r--r--src/soc/intel/broadwell/sata.c6
-rw-r--r--src/soc/intel/broadwell/serialio.c4
-rw-r--r--src/soc/intel/broadwell/systemagent.c6
12 files changed, 111 insertions, 97 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 220ad6f269..06dd38bd8a 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -14,11 +14,11 @@
#include <soc/pch.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
static void adsp_init(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
struct resource *bar0, *bar1;
u32 tmp32;
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 45d512ac02..81c9780776 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -7,70 +7,6 @@
#include <stdint.h>
struct soc_intel_broadwell_config {
- /* GPE configuration */
- uint32_t gpe0_en_1;
- uint32_t gpe0_en_2;
- uint32_t gpe0_en_3;
- uint32_t gpe0_en_4;
-
- /* GPIO SMI configuration */
- uint32_t alt_gp_smi_en;
-
- /* IDE configuration */
- uint8_t sata_port_map;
- uint32_t sata_port0_gen3_tx;
- uint32_t sata_port1_gen3_tx;
- uint32_t sata_port2_gen3_tx;
- uint32_t sata_port3_gen3_tx;
- uint32_t sata_port0_gen3_dtle;
- uint32_t sata_port1_gen3_dtle;
- uint32_t sata_port2_gen3_dtle;
- uint32_t sata_port3_gen3_dtle;
-
- /*
- * SATA DEVSLP Mux
- * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
- * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
- */
- uint8_t sata_devslp_mux;
-
- /*
- * DEVSLP Disable
- * 0: DEVSLP is enabled
- * 1: DEVSLP is disabled
- */
- uint8_t sata_devslp_disable;
-
- /* Generic IO decode ranges */
- uint32_t gen1_dec;
- uint32_t gen2_dec;
- uint32_t gen3_dec;
- uint32_t gen4_dec;
-
- /* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
-
- /* Force root port ASPM configuration with port bitmap */
- uint8_t pcie_port_force_aspm;
-
- /* Put SerialIO devices into ACPI mode instead of a PCI device */
- uint8_t sio_acpi_mode;
-
- /* I2C voltage select: 0=3.3V 1=1.8V */
- uint8_t sio_i2c0_voltage;
- uint8_t sio_i2c1_voltage;
-
- /* Enable ADSP power gating features */
- uint8_t adsp_d3_pg_enable;
- uint8_t adsp_sram_pg_enable;
-
- /*
- * Clock Disable Map:
- * [21:16] = CLKOUT_PCIE# 5-0
- * [24] = CLKOUT_ITPXDP
- */
- uint32_t icc_clock_disable;
-
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -107,9 +43,6 @@ struct soc_intel_broadwell_config {
struct i915_gpu_controller_info gfx;
- /* Enable S0iX support */
- int s0ix_enable;
-
/*
* Minimum voltage for C6/C7 state:
* 0x67 = 1.6V (full swing)
@@ -132,9 +65,8 @@ struct soc_intel_broadwell_config {
/* Enable slow VR ramp rate */
int vr_slow_ramp_rate_enable;
- /* Deep SX enable */
- int deep_sx_enable_ac;
- int deep_sx_enable_dc;
+ /* Enable S0iX support */
+ int s0ix_enable;
/* TCC activation offset */
uint32_t tcc_offset;
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h
index 0b6ef0d61b..5d7eceb4a5 100644
--- a/src/soc/intel/broadwell/include/soc/ramstage.h
+++ b/src/soc/intel/broadwell/include/soc/ramstage.h
@@ -8,7 +8,6 @@
void broadwell_init_pre_device(void *chip_info);
void broadwell_init_cpus(struct device *dev);
-void broadwell_pch_enable_dev(struct device *dev);
#if CONFIG(HAVE_REFCODE_BLOB)
void broadwell_run_reference_code(void);
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 8b85a0420d..2111913a0e 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -24,7 +24,7 @@
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
#include <acpi/acpigen.h>
#include <southbridge/intel/common/rtc.h>
@@ -130,7 +130,7 @@ static void pch_power_options(struct device *dev)
u16 reg16;
const char *state;
/* Get the chip configuration */
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)?
@@ -336,7 +336,7 @@ static void pch_enable_mphy(void)
static void pch_init_deep_sx(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
if (config->deep_sx_enable_ac) {
RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
@@ -567,7 +567,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
/* Add the default claimed IO range for the LPC device. */
res = new_resource(dev, 0);
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 80ffe2b9ac..40a81d8810 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -26,7 +26,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
@@ -950,7 +950,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
/* Check whether ME is present and do basic init */
static void intel_me_init(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
me_bios_path path = intel_me_path(dev);
me_bios_payload mbp_data;
int mbp_ret;
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 2a27d92152..e0c5bb0c4d 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -166,10 +166,16 @@ void pch_disable_devfn(struct device *dev)
}
}
-void broadwell_pch_enable_dev(struct device *dev)
+static void broadwell_pch_enable_dev(struct device *dev)
{
u16 reg16;
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return;
+
+ if (dev->ops && dev->ops->enable)
+ return;
+
/* These devices need special enable/disable handling */
switch (PCI_SLOT(dev->path.pci.devfn)) {
case PCH_DEV_SLOT_PCIE:
@@ -195,4 +201,9 @@ void broadwell_pch_enable_dev(struct device *dev)
}
}
+struct chip_operations soc_intel_broadwell_pch_ops = {
+ CHIP_NAME("Intel Broadwell PCH")
+ .enable_dev = &broadwell_pch_enable_dev,
+};
+
#endif
diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h
new file mode 100644
index 0000000000..2164a31050
--- /dev/null
+++ b/src/soc/intel/broadwell/pch/chip.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_
+#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_
+
+#include <stdint.h>
+
+struct soc_intel_broadwell_pch_config {
+ /* GPE configuration */
+ uint32_t gpe0_en_1;
+ uint32_t gpe0_en_2;
+ uint32_t gpe0_en_3;
+ uint32_t gpe0_en_4;
+
+ /* GPIO SMI configuration */
+ uint32_t alt_gp_smi_en;
+
+ /* IDE configuration */
+ uint8_t sata_port_map;
+ uint32_t sata_port0_gen3_tx;
+ uint32_t sata_port1_gen3_tx;
+ uint32_t sata_port2_gen3_tx;
+ uint32_t sata_port3_gen3_tx;
+ uint32_t sata_port0_gen3_dtle;
+ uint32_t sata_port1_gen3_dtle;
+ uint32_t sata_port2_gen3_dtle;
+ uint32_t sata_port3_gen3_dtle;
+
+ /*
+ * SATA DEVSLP Mux
+ * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
+ * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
+ */
+ uint8_t sata_devslp_mux;
+
+ /*
+ * DEVSLP Disable
+ * 0: DEVSLP is enabled
+ * 1: DEVSLP is disabled
+ */
+ uint8_t sata_devslp_disable;
+
+ /* Generic IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
+
+ /* Enable linear PCIe Root Port function numbers starting at zero */
+ uint8_t pcie_port_coalesce;
+
+ /* Force root port ASPM configuration with port bitmap */
+ uint8_t pcie_port_force_aspm;
+
+ /* Put SerialIO devices into ACPI mode instead of a PCI device */
+ uint8_t sio_acpi_mode;
+
+ /* I2C voltage select: 0=3.3V 1=1.8V */
+ uint8_t sio_i2c0_voltage;
+ uint8_t sio_i2c1_voltage;
+
+ /* Enable ADSP power gating features */
+ uint8_t adsp_d3_pg_enable;
+ uint8_t adsp_sram_pg_enable;
+
+ /*
+ * Clock Disable Map:
+ * [21:16] = CLKOUT_PCIE# 5-0
+ * [24] = CLKOUT_ITPXDP
+ */
+ uint32_t icc_clock_disable;
+
+ /* Deep SX enable */
+ int deep_sx_enable_ac;
+ int deep_sx_enable_dc;
+};
+
+#endif
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 0d41d42525..c98201e5ab 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -13,7 +13,7 @@
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
#include <soc/cpu.h>
#include <delay.h>
@@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev)
root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
rpc.coalesce = config->pcie_port_coalesce;
}
@@ -436,7 +436,7 @@ static void pcie_add_0x0202000_iobp(u32 reg)
static void pch_pcie_early(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
int do_aspm = 0;
int rp = root_port_number(dev);
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index d68e17eee2..149dda1ca0 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -12,7 +12,7 @@
#include <soc/rcba.h>
#include <soc/romstage.h>
#include <soc/smbus.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
static void pch_route_interrupts(void)
{
@@ -52,9 +52,9 @@ static void pch_route_interrupts(void)
static void pch_enable_lpc(void)
{
/* Lookup device tree in romstage */
- const config_t *config;
+ const struct device *const dev = pcidev_on_root(0x1f, 0);
- config = config_of_soc();
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index c9168325e2..b496e53e3d 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -11,7 +11,7 @@
#include <soc/ramstage.h>
#include <soc/rcba.h>
#include <soc/sata.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
static inline u32 sir_read(struct device *dev, int idx)
{
@@ -27,7 +27,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
static void sata_init(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
u32 reg32;
u8 *abar;
u16 reg16;
@@ -256,7 +256,7 @@ static void sata_init(struct device *dev)
static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
u16 map = 0x0060;
map |= (config->sata_port_map ^ 0xf) << 8;
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 766f5dd048..d32a27ddca 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -14,7 +14,7 @@
#include <soc/ramstage.h>
#include <soc/rcba.h>
#include <soc/serialio.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct resource *res)
@@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode)
static void serialio_init(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
struct resource *bar0, *bar1;
int sio_index = -1;
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index dc6f546780..b9aeb388a1 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -472,12 +472,6 @@ static void broadwell_enable(struct device *dev)
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
- } else if (dev->path.type == DEVICE_PATH_PCI) {
- /* Handle PCH device enable */
- if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD &&
- (dev->ops == NULL || dev->ops->enable == NULL)) {
- broadwell_pch_enable_dev(dev);
- }
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 16:23:00 +0000