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-rw-r--r--src/soc/intel/common/block/smm/Kconfig9
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c18
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 035578003a..909382e0ee 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -7,3 +7,12 @@ config SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
bool
help
Intel Processor trap flag if it is supported
+
+config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
+ int
+ default 100 if CHROMEOS
+ default 0
+ help
+ Time in milliseconds that SLP_SMI for S5 waits for before
+ enabling sleep. This is required to avoid any race between
+ SLP_SMI and PWRBTN SMI.
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 81ff3ebec8..d492459dc8 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <delay.h>
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
@@ -219,6 +220,23 @@ void smihandler_southbridge_sleep(
pmc_soc_restore_power_failure();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
+
+ /*
+ * Some platforms (e.g. Chromebooks) have observed race between
+ * SLP SMI and PWRBTN SMI because of the way these SMIs are
+ * triggered on power button press. Allow adding a delay before
+ * triggering sleep enable for S5, so that power button
+ * interrupt does not result into immediate wake.
+ */
+ mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS);
+
+ /*
+ * Ensure any pending power button status bits are cleared as
+ * the system is entering S5 and doesn't want to be woken up
+ * right away from older power button events.
+ */
+ pmc_clear_pm1_status();
+
break;
default:
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");