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-rw-r--r--src/soc/intel/elkhartlake/chip.h3
-rw-r--r--src/soc/intel/elkhartlake/fsp_params.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index b15d78a1ee..e8505f4a37 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -239,6 +239,9 @@ struct soc_intel_elkhartlake_config {
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */
+ uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS];
+
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
uint8_t ScsEmmcDdr50Enabled;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 11fc2d3f75..1b667feb4e 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -381,6 +381,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
!config->PcieRpAdvancedErrorReportingDisable[i];
params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
params->PciePtm[i] = config->PciePtm[i];
+ params->PcieRpPcieSpeed[i] = config->PcieRpPcieSpeed[i];
params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003;
params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
/* Virtual Channel 1 to Traffic Class mapping */