7 files changed, 35 insertions, 61 deletions
diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h
index 5ead89f6dc..0d920fb642 100644
--- a/src/soc/intel/baytrail/baytrail/smm.h
+++ b/src/soc/intel/baytrail/baytrail/smm.h
@@ -31,7 +31,7 @@ static inline int smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *smm_region_start(void);
+uintptr_t smm_region_start(void);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM___)
 #include <stdint.h>
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index f383d82738..f2e14b3c93 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -22,12 +22,12 @@
 #include <baytrail/iosf.h>
 #include <baytrail/smm.h>
 
-void *smm_region_start(void)
+uintptr_t smm_region_start(void)
 {
-	return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
+	return (iosf_bunit_read(BUNIT_SMRRL) << 20);
 }
 
-unsigned long get_top_of_ram(void)
+void *cbmem_top(void)
 {
-	return (unsigned long)smm_region_start();
+	return (void *) smm_region_start();
 }
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 046cc1da07..28f4062a6a 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -23,19 +23,24 @@
 #include <broadwell/pci_devs.h>
 #include <broadwell/systemagent.h>
 
-unsigned long get_top_of_ram(void)
+static uintptr_t dpr_region_start(void)
 {
 	/*
 	 * Base of DPR is top of usable DRAM below 4GiB. The register has
 	 * 1 MiB alignment and reports the TOP of the range, the base
 	 * must be calculated from the size in MiB in bits 11:4.
 	 */
-	u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
-	u32 tom = dpr & ~((1 << 20) - 1);
+	uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
+	uintptr_t tom = dpr & ~((1 << 20) - 1);
 
 	/* Subtract DMA Protected Range size if enabled */
 	if (dpr & DPR_EPM)
 		tom -= (dpr & DPR_SIZE_MASK) << 16;
 
-	return (unsigned long)tom;
+	return tom;
+}
+
+void *cbmem_top(void)
+{
+	return (void *) dpr_region_start();
 }
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index fcbe6e7e9e..3896e851e7 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -44,8 +44,6 @@ ramstage-y += ramstage.c
 ramstage-y += gpio.c
 romstage-y += gpio.c
 ramstage-y += pmutil.c
-romstage-y += raminit.c
-ramstage-y += raminit.c
 ramstage-y += southcluster.c
 romstage-y += reset.c
 ramstage-y += reset.c
diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h
index 0208c9f290..136c2ca66e 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/smm.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h
@@ -36,7 +36,7 @@ static inline int smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *smm_region_start(void);
+uintptr_t smm_region_start(void);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM___)
 #include <stdint.h>
diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c
index 83858b89a8..615916b96d 100644
--- a/src/soc/intel/fsp_baytrail/memmap.c
+++ b/src/soc/intel/fsp_baytrail/memmap.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,8 +22,25 @@
 #include <cbmem.h>
 #include <baytrail/iosf.h>
 #include <baytrail/smm.h>
+#include <drivers/intel/fsp/fsp_util.h>
 
-void *smm_region_start(void)
+uintptr_t smm_region_start(void)
 {
-	return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
+	return (iosf_bunit_read(BUNIT_SMRRL) << 20);
+}
+
+/*
+ * Calculate the top of usable (low) DRAM.
+ * The FSP's reserved memory sits just below the SMM region,
+ * allowing calculation of the top of usable memory.
+ *
+ * The entire memory map is shown in northcluster.c
+ */
+
+void *cbmem_top(void)
+{
+	uintptr_t tom = smm_region_start();
+	if (!tom)
+		tom = iosf_bunit_read(BUNIT_BMBOUND);
+	return (void *) tom - FSP_RESERVE_MEMORY_SIZE;
 }
diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c
deleted file mode 100644
index 55692d2d86..0000000000
--- a/src/soc/intel/fsp_baytrail/raminit.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <cbmem.h>
-#include <device/device.h>
-#include <baytrail/baytrail.h>
-#include <baytrail/iosf.h>
-#include <cpu/x86/msr.h>
-#include <drivers/intel/fsp/fsp_util.h>
-
-unsigned long get_top_of_ram(void)
-{
-	/*
-	 * Calculate the top of usable (low) DRAM.
-	 * The FSP's reserved memory sits just below the SMM region,
-	 * allowing calculation of the top of usable memory.
-	 *
-	 * The entire memory map is shown in northcluster.c
-	 */
-	u32 tom = iosf_bunit_read(BUNIT_BMBOUND);
-	u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20;
-	if (bsmmrrl) {
-		tom = bsmmrrl;
-	}
-	tom -= FSP_RESERVE_MEMORY_SIZE;
-
-	return (unsigned long) tom;
-}