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-rw-r--r--src/soc/intel/cannonlake/Kconfig21
-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/cpu.c8
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c2
4 files changed, 0 insertions, 34 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index a86c4df877..36fa59615b 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -1,25 +1,6 @@
config SOC_INTEL_CANNONLAKE_BASE
bool
-config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
- bool
- default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE
- help
- Single Kconfig option to select common base Cannonlake support.
- This Kconfig will help to select majority of CNL SoC features.
- Major difference that exist today between
- SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
- are in FSP Header Files. Hence this Kconfig might help to select
- required SoC support FSP headers. Any future Intel SoC would
- like to make use of CNL support might just select this Kconfig.
-
-config SOC_INTEL_CANNONLAKE
- bool
- select SOC_INTEL_CANNONLAKE_BASE
- select MICROCODE_BLOB_NOT_IN_BLOB_REPO
- help
- Intel Cannonlake support
-
config SOC_INTEL_COFFEELAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
@@ -89,7 +70,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select HAVE_SMI_HANDLER
- select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
select IDT_IN_EVERY_STAGE
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
@@ -338,7 +318,6 @@ config FSP_HEADER_PATH
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
- default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
config FSP_FD_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2727aa22a7..15592d54fa 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -89,9 +89,6 @@ struct soc_intel_cannonlake_config {
enum {
SaGv_Disabled,
SaGv_FixedLow,
-#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
- SaGv_FixedMid,
-#endif
SaGv_FixedHigh,
SaGv_Enabled,
} SaGv;
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 61b19894eb..f4b72abe75 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -178,14 +178,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
msr_t msr2;
/*
- * CFL and WHL CPU die are based on KBL CPU so we need to
- * have this check, where CNL CPU die is not based on KBL CPU
- * so skip this check for CNL.
- */
- if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS))
- return 0;
-
- /*
* If PRMRR/SGX is supported the FIT microcode load will set the msr
* 0x08b with the Patch revision id one less than the id in the
* microcode binary. The PRMRR support is indicated in the MSR
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 3cd148bc0f..d55741ffb2 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -73,9 +73,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
-#endif
if (config->cpu_ratio_override) {
m_cfg->CpuRatio = config->cpu_ratio_override;