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-rw-r--r--src/soc/mediatek/common/memory.c9
-rw-r--r--src/soc/mediatek/mt8196/Kconfig3
-rw-r--r--src/soc/mediatek/mt8196/Makefile.mk17
-rw-r--r--src/soc/mediatek/mt8196/emi.c13
-rw-r--r--src/soc/mediatek/mt8196/include/soc/dramc_param.h114
-rw-r--r--src/soc/mediatek/mt8196/include/soc/dramc_soc.h51
-rw-r--r--src/soc/mediatek/mt8196/include/soc/emi.h15
7 files changed, 186 insertions, 36 deletions
diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c
index 72ea37eea3..089c6affac 100644
--- a/src/soc/mediatek/common/memory.c
+++ b/src/soc/mediatek/common/memory.c
@@ -5,6 +5,7 @@
#include <cbmem.h>
#include <commonlib/bsd/mem_chip_info.h>
#include <console/console.h>
+#include <fmap_config.h>
#include <soc/dramc_common.h>
#include <mrc_cache.h>
#include <soc/dramc_param.h>
@@ -13,12 +14,8 @@
#include <symbols.h>
#include <timer.h>
-/* This must be defined in chromeos.fmd in same name and size. */
-#define CAL_REGION_RW_MRC_CACHE "RW_MRC_CACHE"
-#define CAL_REGION_RW_MRC_CACHE_SIZE 0x2000
-
-_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_MRC_CACHE_SIZE,
- "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_MRC_CACHE);
+_Static_assert(sizeof(struct dramc_param) <= FMAP_SECTION_RW_MRC_CACHE_SIZE,
+ "sizeof(struct dramc_param) exceeds RW_MRC_CACHE size");
const char *get_dram_geometry_str(u32 ddr_geometry);
const char *get_dram_type_str(u32 ddr_type);
diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig
index d373b956c9..69823e4fa8 100644
--- a/src/soc/mediatek/mt8196/Kconfig
+++ b/src/soc/mediatek/mt8196/Kconfig
@@ -8,6 +8,9 @@ config SOC_MEDIATEK_MT8196
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64
select HAVE_UART_SPECIAL
+ select CACHE_MRC_SETTINGS
+ select MEDIATEK_DRAM_BLOB_FAST_INIT
+ select USE_CBMEM_DRAM_INFO
select SOC_MEDIATEK_COMMON
select FLASH_DUAL_IO_READ
select ARM64_USE_ARCH_TIMER
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index f67ef0c8c8..b0eb693d54 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -18,14 +18,18 @@ bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c
bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
romstage-y += ../common/cbmem.c
+romstage-y += ../common/dram_init.c
+romstage-y += ../common/dramc_param.c
romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c
-romstage-y += emi.c
+romstage-y += ../common/emi.c
romstage-y += irq2axi.c
romstage-y += l2c_ops.c
+romstage-y += ../common/memory.c
+romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-y += ../common/early_init.c
-ramstage-y += emi.c
+ramstage-y += ../common/emi.c
ramstage-y += l2c_ops.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c
@@ -35,6 +39,15 @@ ramstage-y += ../common/usb.c usb.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+MT8196_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8196
+
+DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
+$(DRAM_CBFS)-file := $(MT8196_BLOB_DIR)/dram.elf
+$(DRAM_CBFS)-type := stage
+$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
+ cbfs-files-y += $(DRAM_CBFS)
+endif
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
./util/mtkheader/gen-bl-img.py mt8196 sf $< $@
diff --git a/src/soc/mediatek/mt8196/emi.c b/src/soc/mediatek/mt8196/emi.c
deleted file mode 100644
index 1129ce13bb..0000000000
--- a/src/soc/mediatek/mt8196/emi.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 10.2
- */
-
-#include <soc/emi.h>
-
-size_t sdram_size(void)
-{
- return (size_t)4 * GiB;
-}
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
new file mode 100644
index 0000000000..b35d518720
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__
+#define __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__
+
+/*
+ * NOTE: This file is shared between coreboot and dram blob. Any change in this
+ * file should be synced to the other repository.
+ */
+
+#include <soc/dramc_param_common.h>
+#include <soc/dramc_soc.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#define DRAMC_PARAM_HEADER_VERSION 2
+
+struct sdram_params {
+ /* rank, cbt */
+ u32 rank_num;
+ u32 dram_cbt_mode;
+
+ u16 delay_cell_timex100;
+ u8 u18ph_dly;
+
+ /* duty */
+ s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+ s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+ s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+ s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1];
+ s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+ s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+ /* cbt */
+ u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
+ s16 cbt_cmd_dly[CHANNEL_MAX];
+ u16 cbt_cs_dly[CHANNEL_MAX];
+ u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
+
+ /* write leveling */
+ u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+ /* gating */
+ u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+ /* rx input buffer */
+ s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5];
+ s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+ /* tx perbit */
+ u16 tx_window_vref[CHANNEL_MAX][RANK_MAX];
+ u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
+ u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH];
+ u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX];
+ u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX];
+
+ /* rx datlat */
+ u8 rx_datlat[CHANNEL_MAX];
+
+ /* rx perbit */
+ u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+ u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+ s16 rx_perbit_begin;
+
+ /* dvs */
+ u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+ u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+
+ /* dcm */
+ u8 best_u[CHANNEL_MAX][RANK_MAX];
+ u8 best_l[CHANNEL_MAX][RANK_MAX];
+
+ /* Read DCA */
+ s8 rdca_u[CHANNEL_MAX][RANK_MAX];
+ s8 rdca_l[CHANNEL_MAX][RANK_MAX];
+
+ /* RDCC */
+ s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+ /* tx oe */
+ u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+ u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
+};
+
+struct dramc_data {
+ struct ddr_base_info ddr_info;
+ struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+};
+
+struct dramc_param {
+ struct dramc_param_header header;
+ void (*do_putc)(unsigned char c);
+ struct dramc_data dramc_datas;
+};
+
+struct dramc_param *get_dramc_param_from_blob(void *blob);
+void dump_param_header(const void *blob);
+int validate_dramc_param(const void *blob);
+int is_valid_dramc_param(const void *blob);
+int initialize_dramc_param(void *blob);
+
+#endif /* __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
new file mode 100644
index 0000000000..dde00c23da
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__
+
+#include <soc/dramc_soc_common.h>
+#include <stdint.h>
+
+typedef enum {
+ CHANNEL_A = 0,
+ CHANNEL_B,
+ CHANNEL_C,
+ CHANNEL_D,
+ CHANNEL_MAX,
+} DRAM_CHANNEL_T;
+
+typedef enum {
+ RANK_0 = 0,
+ RANK_1,
+ RANK_MAX,
+} DRAM_RANK_T;
+
+typedef enum {
+ SRAM_SHU0 = 0,
+ SRAM_SHU1,
+ SRAM_SHU2,
+ SRAM_SHU3,
+ SRAM_SHU4,
+ SRAM_SHU5,
+ SRAM_SHU6,
+ SRAM_SHU7,
+ SRAM_SHU8,
+ SRAM_SHU9,
+ SRAM_SHU10,
+ SRAM_SHU11,
+ DRAM_DFS_SRAM_MAX
+} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */
+
+typedef enum {
+ DRVP = 0,
+ DRVN,
+ ODTN,
+ IMP_DRV_MAX,
+} DRAM_IMP_DRV_T;
+
+#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX
+#define DQS_NUMBER_LP5 2
+#define DQ_DATA_WIDTH_LP5 16
+#define EXT_DQ_DATA_WIDTH 18
+
+#endif /* __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/emi.h b/src/soc/mediatek/mt8196/include/soc/emi.h
deleted file mode 100644
index 6acc0cfb46..0000000000
--- a/src/soc/mediatek/mt8196/include/soc/emi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 10.2
- */
-
-#ifndef SOC_MEDIATEK_MT8196_EMI_H
-#define SOC_MEDIATEK_MT8196_EMI_H
-
-#include <stddef.h>
-
-size_t sdram_size(void);
-
-#endif /* SOC_MEDIATEK_MT8196_EMI_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 02:26:15 +0000