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-rw-r--r--src/soc/intel/alderlake/chip.h2
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 8ee36f63bc..7934a8635a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -484,7 +484,7 @@ struct soc_intel_alderlake_config {
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
- uint16_t max_dram_speed;
+ uint16_t max_dram_speed_mts;
enum {
SLP_S3_ASSERTION_DEFAULT,
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 83ce074506..863fc43ffa 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -141,8 +141,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
{
m_cfg->SaGv = config->sagv;
m_cfg->RMT = config->RMT;
- if (config->max_dram_speed)
- m_cfg->DdrFreqLimit = config->max_dram_speed;
+ if (config->max_dram_speed_mts)
+ m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
}
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,