diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 5e0e1a6d6d..9a108c95fb 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -30,6 +30,7 @@ config SOC_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select PROVIDES_ROM_SHARING select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON @@ -195,6 +196,14 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 150 +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index b00f49dd97..4e7d84d389 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -60,6 +60,9 @@ void fch_early_init(void) fch_print_pmxc0_status(); i2c_soc_early_init(); + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { espi_setup(); espi_configure_decodes(); |