3 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 1017d80c65..cc111da485 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -35,6 +35,7 @@ ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-y += emmc.c
 ramstage-y += gpio.c
 ramstage-y += gfx.c
+ramstage-y += smbus.c
 
 ramstage-y += gpio_support.c
 ramstage-y += iosf.c
diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h
new file mode 100644
index 0000000000..8bc62f7eec
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/smbus.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
+
+/* PCI Configuration Space SMBus */
+#define HOSTC			0x40
+#define HOSTC_I2C_EN		(1 << 2)
+
+int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf);
+#endif /* _SOC_SMBUS_H_ */
diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c
index 7e1b0dfbb0..1dfd4c7ecd 100644
--- a/src/soc/intel/braswell/smbus.c
+++ b/src/soc/intel/braswell/smbus.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2017 Intel Corporation.
  * Copyright (C) 2019 3mdeb
+ * Copyright (C) 2019 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,6 +17,11 @@
 
 #include <device/early_smbus.h>
 #include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <device/pci_def.h>
+#include <device/pci_type.h>
+#include <device/pci_ops.h>
+#include <soc/smbus.h>
 #include <southbridge/intel/common/smbus.h>
 
 u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
@@ -27,3 +33,29 @@ u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
 {
 	return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
 }
+
+int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
+{
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#else
+	struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
+#endif
+	u32 smbase;
+	u32 smb_ctrl_reg;
+	int status;
+
+	/* SMBus I/O BAR */
+	smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
+
+	/* Enable I2C_EN bit in HOSTC register */
+	smb_ctrl_reg = pci_read_config32(dev, HOSTC);
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
+
+	status = do_i2c_block_write(smbase, addr, bytes, buf);
+
+	/* Restore I2C_EN bit */
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg);
+
+	return status;
+}