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-rw-r--r--src/soc/intel/broadwell/include/soc/gpio.h173
-rw-r--r--src/soc/intel/broadwell/pch/gpio.c2
-rw-r--r--src/soc/intel/broadwell/pch/lpc.c2
-rw-r--r--src/soc/intel/broadwell/pch/pcie.c2
-rw-r--r--src/soc/intel/broadwell/pch/pmutil.c4
-rw-r--r--src/soc/intel/broadwell/romstage.c2
6 files changed, 8 insertions, 177 deletions
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
index 990b7b8e43..05f03ba239 100644
--- a/src/soc/intel/broadwell/include/soc/gpio.h
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -8,177 +8,6 @@
#define CROS_GPIO_DEVICE_NAME "PCH-LP"
#define CROS_GPIO_ACPI_DEVICE_NAME "INT3437:00"
-/* PCH-LP GPIOBASE Registers */
-#define GPIO_OWNER(set) (0x00 + ((set) * 4))
-#define GPIO_PIRQ_APIC_EN 0x10
-#define GPIO_BLINK 0x18
-#define GPIO_SER_BLINK 0x1c
-#define GPIO_SER_BLINK_CS 0x20
-#define GPIO_SER_BLINK_DATA 0x24
-#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
-#define GPIO_ALT_GPI_SMI_STS 0x50
-#define GPIO_ALT_GPI_SMI_EN 0x54
-#define GPIO_RESET(set) (0x60 + ((set) * 4))
-#define GPIO_GLOBAL_CONFIG 0x7c
-#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
-#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
-#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
-#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
-
-#define MAX_GPIO_NUMBER 94 /* zero based */
-#define GPIO_LIST_END 0xffffffff
-
-/* conf0 */
-
-#define GPIO_MODE_NATIVE (0 << 0)
-#define GPIO_MODE_GPIO (1 << 0)
-
-#define GPIO_DIR_OUTPUT (0 << 2)
-#define GPIO_DIR_INPUT (1 << 2)
-
-#define GPIO_NO_INVERT (0 << 3)
-#define GPIO_INVERT (1 << 3)
-
-#define GPIO_IRQ_EDGE (0 << 4)
-#define GPIO_IRQ_LEVEL (1 << 4)
-
-#define GPI_LEVEL (1 << 30)
-
-#define GPIO_OUT_LOW 0
-#define GPIO_OUT_HIGH 1
-#define GPO_LEVEL_SHIFT 31
-#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_LOW (GPIO_OUT_LOW << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_HIGH (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT)
-
-/* conf1 */
-
-#define GPIO_PULL_NONE (0 << 0)
-#define GPIO_PULL_DOWN (1 << 0)
-#define GPIO_PULL_UP (2 << 0)
-
-#define GPIO_SENSE_ENABLE (0 << 2)
-#define GPIO_SENSE_DISABLE (1 << 2)
-
-/* owner */
-
-#define GPIO_OWNER_ACPI 0
-#define GPIO_OWNER_GPIO 1
-
-/* route */
-
-#define GPIO_ROUTE_SCI 0
-#define GPIO_ROUTE_SMI 1
-
-/* irqen */
-
-#define GPIO_IRQ_DISABLE 0
-#define GPIO_IRQ_ENABLE 1
-
-/* blink */
-
-#define GPO_NO_BLINK 0
-#define GPO_BLINK 1
-
-/* reset */
-
-#define GPIO_RESET_PWROK 0
-#define GPIO_RESET_RSMRST 1
-
-/* pirq route to io-apic */
-
-#define GPIO_PIRQ_APIC_MASK 0
-#define GPIO_PIRQ_APIC_ROUTE 1
-
-#define PCH_GPIO_END \
- { .conf0 = GPIO_LIST_END }
-
-#define PCH_GPIO_NATIVE \
- { .conf0 = GPIO_MODE_NATIVE }
-
-#define PCH_GPIO_UNUSED \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-#define PCH_GPIO_ACPI_SCI \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_ACPI, \
- .route = GPIO_ROUTE_SCI }
-
-#define PCH_GPIO_ACPI_SMI \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_ACPI, \
- .route = GPIO_ROUTE_SMI }
-
-#define PCH_GPIO_INPUT \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO }
-
-#define PCH_GPIO_INPUT_INVERT \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_GPIO }
-
-#define PCH_GPIO_IRQ_EDGE \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
- .owner = GPIO_OWNER_GPIO, \
- .irqen = GPIO_IRQ_ENABLE }
-
-#define PCH_GPIO_IRQ_LEVEL \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
- .owner = GPIO_OWNER_GPIO, \
- .irqen = GPIO_IRQ_ENABLE }
-
-#define PCH_GPIO_PIRQ \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO, \
- .pirq = GPIO_PIRQ_APIC_ROUTE }
-
-#define PCH_GPIO_PIRQ_INVERT \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_GPIO, \
- .pirq = GPIO_PIRQ_APIC_ROUTE }
-
-#define PCH_GPIO_OUT_HIGH \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-#define PCH_GPIO_OUT_LOW \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-struct pch_lp_gpio_map {
- u8 gpio;
- u32 conf0;
- u32 conf1;
- u8 owner;
- u8 route;
- u8 irqen;
- u8 reset;
- u8 blink;
- u8 pirq;
-} __packed;
-
-/* Configure GPIOs with mainboard provided settings */
-void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
-
-/* Get GPIO pin value */
-int get_gpio(int gpio_num);
-
-/* Set GPIO pin value */
-void set_gpio(int gpio_num, int value);
-
-/* Return non-zero if gpio is set to native function. 0 otherwise. */
-int gpio_is_native(int gpio_num);
-
-/*
- * Get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array);
-
-extern const struct pch_lp_gpio_map mainboard_gpio_map[];
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#endif
diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/soc/intel/broadwell/pch/gpio.c
index 952329117e..a1c8345d3b 100644
--- a/src/soc/intel/broadwell/pch/gpio.c
+++ b/src/soc/intel/broadwell/pch/gpio.c
@@ -4,9 +4,9 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/pm.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
/*
* This function will return a number that indicates which PIRQ
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 873e57e12a..377a4da77a 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -13,7 +13,6 @@
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <string.h>
-#include <soc/gpio.h>
#include <soc/iobp.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -26,6 +25,7 @@
#include <soc/intel/broadwell/pch/chip.h>
#include <acpi/acpigen.h>
#include <southbridge/intel/common/rtc.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
static void pch_enable_ioapic(struct device *dev)
{
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index 141fc14168..7f16cb4d2c 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -8,13 +8,13 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/iobp.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/rcba.h>
#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <delay.h>
/* Low Power variant has 6 root ports. */
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index be383277e5..59ae72f3fc 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -17,10 +17,12 @@
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/gpio.h>
#include <security/vboot/vbnv.h>
#include <stdint.h>
+#define GPIO_ALT_GPI_SMI_STS 0x50
+#define GPIO_ALT_GPI_SMI_EN 0x54
+
static inline uint16_t get_gpiobase(void)
{
return GPIO_BASE_ADDRESS;
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c
index b9570f3e68..12072a3a50 100644
--- a/src/soc/intel/broadwell/romstage.c
+++ b/src/soc/intel/broadwell/romstage.c
@@ -8,12 +8,12 @@
#include <cpu/intel/haswell/haswell.h>
#include <elog.h>
#include <romstage_handoff.h>
-#include <soc/gpio.h>
#include <soc/me.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/romstage.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <stdint.h>
#include <timestamp.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 05:12:50 +0000