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-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h55
-rw-r--r--src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h54
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h54
3 files changed, 58 insertions, 105 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 54b76b5719..f29991de0e 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -3,20 +3,10 @@
#ifndef _SOC_PCI_DEVS_H_
#define _SOC_PCI_DEVS_H_
+#include <device/device.h>
#include <device/pci_def.h>
#include <types.h>
-
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
-
-#if !defined(__SIMPLE_DEVICE__)
-#include <device/device.h>
-#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
-#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
-#else
-#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
-#endif
+#include <soc/pch_pci_devs.h>
#define SAD_ALL_DEV 29
#define SAD_ALL_FUNC 0
@@ -132,47 +122,6 @@
#define DEVICES_PER_IIO_STACK 4
-/* PCH Device info */
-
-#define XHCI_BUS_NUMBER 0x0
-#define PCH_DEV_SLOT_XHCI 0x14
-#define XHCI_FUNC_NUM 0x0
-#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
-#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
-#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
-
-
-#define PCH_DEV_SLOT_CSE 0x16
-#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
-#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
-#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
-#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
-#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
-#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
-
-#define PCH_DEV_SLOT_LPC 0x1f
-#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
-#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
-#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
-#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
-#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
-#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
-#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
-#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
-#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
-#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
-
-#define HPET_BUS_NUM 0x0
-#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
-#define HPET0_FUNC_NUM 0x00
-
-#define PCH_IOAPIC_BUS_NUMBER 0xF0
-#define PCH_IOAPIC_DEV_NUM 0x1F
-#define PCH_IOAPIC_FUNC_NUM 0x00
-
-// ========== IOAPIC Definitions for DMAR/ACPI ========
-#define PCH_IOAPIC_ID 0x08
-
// DMI3 B0D0F0 registers
#define DMI3_DEVID 0x2020
#define DMIRCBAR 0x50
diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h
new file mode 100644
index 0000000000..41ec7e1450
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PCH_PCI_DEVS_H_
+#define _SOC_PCH_PCI_DEVS_H_
+
+#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if !defined(__SIMPLE_DEVICE__)
+#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
+#else
+#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+/* PCH Device info */
+
+#define XHCI_BUS_NUMBER 0x0
+#define PCH_DEV_SLOT_XHCI 0x14
+#define XHCI_FUNC_NUM 0x0
+#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
+#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
+#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
+
+#define HPET_BUS_NUM 0x0
+#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
+#define HPET0_FUNC_NUM 0x00
+
+#define PCH_DEV_SLOT_CSE 0x16
+#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
+#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
+#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
+#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
+#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
+#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
+
+#define PCH_DEV_SLOT_LPC 0x1f
+#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
+#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
+#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
+#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
+#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
+#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
+#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
+#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
+#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
+#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+
+#define PCH_IOAPIC_BUS_NUMBER 0xF0
+#define PCH_IOAPIC_DEV_NUM 0x1F
+#define PCH_IOAPIC_FUNC_NUM 0x00
+
+// ========== IOAPIC Definitions for DMAR/ACPI ========
+#define PCH_IOAPIC_ID 0x08
+
+#endif
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 3d71045236..525ec3c91b 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -4,8 +4,10 @@
#define _SOC_PCI_DEVS_H_
#include <console/console.h>
+#include <device/device.h>
#include <device/pci_def.h>
#include <hob_iiouds.h>
+#include <soc/pch_pci_devs.h>
#define dump_csr(fmt, dev, reg) \
printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
@@ -19,18 +21,6 @@
((uint32_t)dev >> 12) & 0x07, #reg, reg, \
pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg))
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
-
-#if !defined(__SIMPLE_DEVICE__)
-#include <device/device.h>
-#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
-#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
-#else
-#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
-#endif
-
#define SAD_ALL_DEV 29
#define SAD_ALL_FUNC 0
#define SAD_ALL_PAM0123_CSR 0x40
@@ -118,19 +108,6 @@
#define CHA_UTIL_ALL_FUNC 1
#define CHA_UTIL_ALL_MMCFG_CSR 0xc0
-/* PCH Device info */
-
-#define XHCI_BUS_NUMBER 0x0
-#define PCH_DEV_SLOT_XHCI 0x14
-#define XHCI_FUNC_NUM 0x0
-#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
-#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
-#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
-
-#define HPET_BUS_NUM 0x0
-#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
-#define HPET0_FUNC_NUM 0x00
-
#define MMAP_VTD_CFG_REG_DEVID 0x2024
#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034
#define VTD_DEV_NUM 0x5
@@ -142,26 +119,6 @@
#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
#endif
-#define PCH_DEV_SLOT_CSE 0x16
-#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
-#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
-#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
-#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
-#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
-#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
-
-#define PCH_DEV_SLOT_LPC 0x1f
-#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
-#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
-#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
-#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
-#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
-#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
-#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
-#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
-#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
-#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
-
#define CBDMA_DEV_NUM 0x04
#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function
#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB
@@ -172,13 +129,6 @@
#define APIC_DEV_NUM 0x05
#define APIC_FUNC_NUM 0x00
-#define PCH_IOAPIC_BUS_NUMBER 0xF0
-#define PCH_IOAPIC_DEV_NUM 0x1F
-#define PCH_IOAPIC_FUNC_NUM 0x00
-
-// ========== IOAPIC Definitions for DMAR/ACPI ========
-#define PCH_IOAPIC_ID 0x08
-
// DMI3 B0D0F0 registers
#define DMI3_DEVID 0x2020
#define DMIRCBAR 0x50
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 04:15:34 +0000