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-rw-r--r--src/soc/nvidia/tegra124/display.c9
-rw-r--r--src/soc/nvidia/tegra132/dc.c12
-rw-r--r--src/soc/nvidia/tegra210/dc.c12
-rw-r--r--src/soc/rockchip/rk3288/display.c6
4 files changed, 16 insertions, 23 deletions
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index ac1b950b0b..74202bad23 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -331,10 +331,9 @@ void display_startup(device_t dev)
/* tell depthcharge ...
*/
struct edid edid;
- edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) /
- 32 * 32);
- edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8);
- edid.y_resolution = config->yres;
- edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
+ edid.mode.va = config->yres;
+ edid.mode.ha = config->xres;
+ edid_set_framebuffer_bits_per_pixel(&edid,
+ config->framebuffer_bits_per_pixel);
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));
}
diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c
index 2b1687b631..562061a1d3 100644
--- a/src/soc/nvidia/tegra132/dc.c
+++ b/src/soc/nvidia/tegra132/dc.c
@@ -226,13 +226,11 @@ void pass_mode_info_to_payload(
struct soc_nvidia_tegra132_config *config)
{
struct edid edid;
- /* Align bytes_per_line to 64 bytes as required by dc */
- edid.bytes_per_line = ALIGN_UP((config->display_xres *
- config->framebuffer_bits_per_pixel / 8), 64);
- edid.x_resolution = edid.bytes_per_line /
- (config->framebuffer_bits_per_pixel / 8);
- edid.y_resolution = config->display_yres;
- edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
+
+ edid.mode.va = config->display_yres;
+ edid.mode.ha = config->display_xres;
+ edid_set_framebuffer_bits_per_pixel(&edid,
+ config->framebuffer_bits_per_pixel);
printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
" x_res x y_res: %d x %d, size: %d\n",
diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c
index 5dad92e6b8..72f1bcb3fa 100644
--- a/src/soc/nvidia/tegra210/dc.c
+++ b/src/soc/nvidia/tegra210/dc.c
@@ -226,13 +226,11 @@ void pass_mode_info_to_payload(
struct soc_nvidia_tegra210_config *config)
{
struct edid edid;
- /* Align bytes_per_line to 64 bytes as required by dc */
- edid.bytes_per_line = ALIGN_UP((config->display_xres *
- config->framebuffer_bits_per_pixel / 8), 64);
- edid.x_resolution = edid.bytes_per_line /
- (config->framebuffer_bits_per_pixel / 8);
- edid.y_resolution = config->display_yres;
- edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
+
+ edid.mode.va = config->display_yres;
+ edid.mode.ha = config->display_xres;
+ edid_set_framebuffer_bits_per_pixel(&edid,
+ config->framebuffer_bits_per_pixel);
printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
" x_res x y_res: %d x %d, size: %d\n",
diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c
index 56eea076f8..66b2edc5b8 100644
--- a/src/soc/rockchip/rk3288/display.c
+++ b/src/soc/rockchip/rk3288/display.c
@@ -94,10 +94,8 @@ void rk_display_init(device_t dev, u32 lcdbase,
return;
}
- edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel;
- edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8;
- edid.x_resolution = edid.mode.ha;
- edid.y_resolution = edid.mode.va;
+ edid_set_framebuffer_bits_per_pixel(&edid,
+ conf->framebuffer_bits_per_pixel);
rkvop_mode_set(conf->vop_id, &edid, detected_mode);
rkvop_enable(conf->vop_id, lcdbase, &edid);