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-rw-r--r--src/soc/intel/skylake/Makefile.inc3
-rw-r--r--src/soc/intel/skylake/pmutil.c20
2 files changed, 22 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index bf429ef902..1714572f0a 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -30,7 +30,8 @@ bootblock-y += tsc_freq.c
verstage-y += flash_controller.c
verstage-y += monotonic_timer.c
verstage-y += pch.c
-verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
+verstage-y += pmutil.c
+verstage-y += bootblock/i2c.c
romstage-y += flash_controller.c
romstage-y += gpio.c
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 31de242752..904be5c2a0 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -351,6 +351,26 @@ u32 clear_gpe_status(void)
gpe0_sts_3_bits);
}
+/* Read and clear GPE status (defined in arch/acpi.h) */
+int acpi_get_gpe(int gpe)
+{
+ int bank;
+ uint32_t mask, sts;
+
+ if (gpe < 0 || gpe > GPE0_WADT)
+ return -1;
+
+ bank = gpe / 32;
+ mask = 1 << (gpe % 32);
+
+ sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
+ if (sts & mask) {
+ outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
+ return 1;
+ }
+ return 0;
+}
+
/* Enable all requested GPE */
void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
{