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-rw-r--r--src/soc/amd/picasso/ramtop.c36
-rw-r--r--src/soc/amd/stoneyridge/ramtop.c35
-rw-r--r--src/soc/intel/apollolake/memmap.c29
-rw-r--r--src/soc/intel/braswell/memmap.c38
-rw-r--r--src/soc/intel/cannonlake/memmap.c47
-rw-r--r--src/soc/intel/denverton_ns/memmap.c30
-rw-r--r--src/soc/intel/icelake/memmap.c47
-rw-r--r--src/soc/intel/skylake/memmap.c47
8 files changed, 6 insertions, 303 deletions
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index 672fdd8194..09af7e4de7 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -81,12 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void smm_region(uintptr_t *start, size_t *size)
-{
- *start = smm_region_start();
- *size = smm_region_size();
-}
-
/*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM.
@@ -109,39 +103,15 @@ static void clear_tvalid(void)
wrmsr(SMM_MASK_MSR, mask);
}
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
static int once;
- uintptr_t sub_base;
- size_t sub_size;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
- smm_region(&sub_base, &sub_size);
- assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+ *start = smm_region_start();
+ *size = smm_region_size();
if (!once) {
clear_tvalid();
once = 1;
}
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - cache_size;
- sub_size = cache_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = (void *)sub_base;
- *size = sub_size;
-
- return 0;
}
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index e2b0f7d6bc..09af7e4de7 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -81,12 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void smm_region(uintptr_t *start, size_t *size)
-{
- *start = smm_region_start();
- *size = smm_region_size();
-}
-
/*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM.
@@ -109,38 +103,15 @@ static void clear_tvalid(void)
wrmsr(SMM_MASK_MSR, mask);
}
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
static int once;
- uintptr_t sub_base;
- size_t sub_size;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
- smm_region(&sub_base, &sub_size);
- assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+ *start = smm_region_start();
+ *size = smm_region_size();
if (!once) {
clear_tvalid();
once = 1;
}
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - cache_size;
- sub_size = cache_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
}
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 17dfb3f545..0eb66dcb40 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -48,32 +48,3 @@ void smm_region(uintptr_t *start, size_t *size)
*start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
-
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - cache_size;
- sub_size = cache_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 51b7b36db4..b4c69a4258 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -34,44 +34,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = smm_region_size();
}
-/*
- * Subregions within SMM
- * +-------------------------+ BUNIT_SMRRH
- * | External Stage Cache | SMM_RESERVED_SIZE
- * +-------------------------+
- * | code and data |
- * | (TSEG) |
- * +-------------------------+ BUNIT_SMRRL
- */
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - cache_size;
- sub_size = cache_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
-
void *cbmem_top(void)
{
uintptr_t smm_base;
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 004e35c98c..a842ff63ec 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -35,53 +35,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size();
}
-/*
- * Subregions within SMM
- * +-------------------------+ BGSM
- * | IED | IED_REGION_SIZE
- * +-------------------------+
- * | External Stage Cache | SMM_RESERVED_SIZE
- * +-------------------------+
- * | code and data |
- * | (TSEG) |
- * +-------------------------+ TSEG
- */
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t ied_size = CONFIG_IED_REGION_SIZE;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= ied_size;
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - (ied_size + cache_size);
- sub_size = cache_size;
- break;
- case SMM_SUBREGION_CHIPSET:
- /* IED is at the top. */
- sub_base += sub_size - ied_size;
- sub_size = ied_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
-
/* Calculate ME Stolen size */
static size_t get_imr_size(void)
{
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 9507d7f238..0cca4b90d4 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -75,33 +75,3 @@ void smm_region(uintptr_t *start, size_t *size)
*start = smm_region_start();
*size = smm_region_size();
}
-
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
- assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - cache_size;
- sub_size = cache_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 13eb947935..e0d7d68fe6 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -33,53 +33,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size();
}
-/*
- * Subregions within SMM
- * +-------------------------+ BGSM
- * | IED | IED_REGION_SIZE
- * +-------------------------+
- * | External Stage Cache | SMM_RESERVED_SIZE
- * +-------------------------+
- * | code and data |
- * | (TSEG) |
- * +-------------------------+ TSEG
- */
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t ied_size = CONFIG_IED_REGION_SIZE;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= ied_size;
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - (ied_size + cache_size);
- sub_size = cache_size;
- break;
- case SMM_SUBREGION_CHIPSET:
- /* IED is at the top. */
- sub_base += sub_size - ied_size;
- sub_size = ied_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
-
/* Calculate ME Stolen size */
static size_t get_imr_size(void)
{
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 963a5003e8..e4e25161c3 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -37,53 +37,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size();
}
-/*
- * Subregions within SMM
- * +-------------------------+ BGSM
- * | IED | IED_REGION_SIZE
- * +-------------------------+
- * | External Stage Cache | SMM_RESERVED_SIZE
- * +-------------------------+
- * | code and data |
- * | (TSEG) |
- * +-------------------------+ TSEG
- */
-int smm_subregion(int sub, uintptr_t *start, size_t *size)
-{
- uintptr_t sub_base;
- size_t sub_size;
- const size_t ied_size = CONFIG_IED_REGION_SIZE;
- const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- smm_region(&sub_base, &sub_size);
-
- switch (sub) {
- case SMM_SUBREGION_HANDLER:
- /* Handler starts at the base of TSEG. */
- sub_size -= ied_size;
- sub_size -= cache_size;
- break;
- case SMM_SUBREGION_CACHE:
- /* External cache is in the middle of TSEG. */
- sub_base += sub_size - (ied_size + cache_size);
- sub_size = cache_size;
- break;
- case SMM_SUBREGION_CHIPSET:
- /* IED is at the top. */
- sub_base += sub_size - ied_size;
- sub_size = ied_size;
- break;
- default:
- *start = 0;
- *size = 0;
- return -1;
- }
-
- *start = sub_base;
- *size = sub_size;
- return 0;
-}
-
static bool is_ptt_enable(void)
{
if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
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