2 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 69459e7e03..66dae8c73c 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -16,6 +16,7 @@
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pmclib.h>
 #include <intelpch/lockdown.h>
 #include <soc/pm.h>
 
@@ -38,6 +39,9 @@ static void pmc_lockdown_config(void)
 	pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
 	pmsyncreg |= PMSYNC_LOCK;
 	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+
+	/* Make sure payload/OS can't trigger global reset */
+	pmc_global_reset_disable_and_lock();
 }
 
 void soc_lockdown_config(int chipset_lockdown)
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index ff1a959194..8f5bf30946 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -26,7 +26,7 @@ static void do_force_global_reset(void)
 	/*
 	 * BIOS should ensure it does a global reset
 	 * to reset both host and Intel ME by setting
-	 * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
+	 * PCH PMC [B0:D31:F2 register offset 0xAC bit 20]
 	 */
 	pmc_global_reset_enable(true);