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-rw-r--r--src/soc/mediatek/common/include/soc/timer.h40
-rw-r--r--src/soc/mediatek/common/include/soc/timer_common.h23
-rw-r--r--src/soc/mediatek/common/include/soc/timer_v1.h34
-rw-r--r--src/soc/mediatek/common/include/soc/timer_v2.h33
-rw-r--r--src/soc/mediatek/common/timer.c12
-rw-r--r--src/soc/mediatek/mt8173/include/soc/timer.h8
-rw-r--r--src/soc/mediatek/mt8183/include/soc/timer.h8
-rw-r--r--src/soc/mediatek/mt8192/include/soc/timer.h8
-rw-r--r--src/soc/mediatek/mt8195/Makefile.inc8
-rw-r--r--src/soc/mediatek/mt8195/include/soc/addressmap.h1
-rw-r--r--src/soc/mediatek/mt8195/include/soc/timer.h20
-rw-r--r--src/soc/mediatek/mt8195/timer.c11
12 files changed, 158 insertions, 48 deletions
diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h
deleted file mode 100644
index 1ebee8f04e..0000000000
--- a/src/soc/mediatek/common/include/soc/timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_COMMON_TIMER_H
-#define SOC_MEDIATEK_COMMON_TIMER_H
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define GPT_MHZ 13
-
-struct mtk_gpt_regs {
- u32 reserved1[24];
- u32 gpt6_con;
- u32 gpt6_clk;
- u32 gpt6_cnt_l;
- u32 reserved2[3];
- u32 gpt6_cnt_h;
-};
-
-check_member(mtk_gpt_regs, gpt6_con, 0x0060);
-check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
-check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
-check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
-
-enum {
- GPT_CON_EN = 0x01,
- GPT_CON_CLR = 0x02,
- GPT_MODE_FREERUN = 0x30,
- GPT_SYS_CLK = 0x00,
- GPT_CLK_DIV1 = 0x00,
-};
-
-/*
- * This is defined as weak no-ops that can be overridden by legacy SOCs. Some
- * legacy SOCs need specific settings before init timer. And we expect future
- * SOCs will not need it.
- */
-void timer_prepare(void);
-
-#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_common.h b/src/soc/mediatek/common/include/soc/timer_common.h
new file mode 100644
index 0000000000..40d150b3f6
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_common.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_COMMON_H
+#define SOC_MEDIATEK_COMMON_TIMER_COMMON_H
+
+#include <types.h>
+
+enum {
+ GPT6_CON_EN = BIT(0),
+ GPT6_CON_CLR = BIT(1),
+ GPT6_MODE_FREERUN = 3,
+ GPT6_CLK_CLK6_SYS = 0,
+ GPT6_CLK_CLKDIV_DIV1 = 0,
+};
+
+/*
+ * This is defined as weak no-ops that can be overridden by legacy SOCs. Some
+ * legacy SOCs need specific settings before init timer. And we expect future
+ * SOCs will not need it.
+ */
+void timer_prepare(void);
+
+#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_v1.h b/src/soc/mediatek/common/include/soc/timer_v1.h
new file mode 100644
index 0000000000..8d64b5d163
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_v1.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_V1_H
+#define SOC_MEDIATEK_COMMON_TIMER_V1_H
+
+#include <device/mmio.h>
+#include <soc/timer_common.h>
+#include <types.h>
+
+#define GPT_MHZ 13
+
+struct mtk_gpt_regs {
+ u32 reserved1[24];
+ u32 gpt6_con;
+ u32 gpt6_clk;
+ u32 gpt6_cnt_l;
+ u32 reserved2[3];
+ u32 gpt6_cnt_h;
+};
+
+check_member(mtk_gpt_regs, gpt6_con, 0x0060);
+check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
+
+DEFINE_BIT(GPT6_CON_EN6, 0)
+DEFINE_BIT(GPT6_CON_CLR6, 1)
+DEFINE_BITFIELD(GPT6_CON_MODE6, 5, 4)
+
+#define GPT6_CLOCK_REG(x) x->gpt6_clk
+DEFINE_BITFIELD(GPT6_CLK_CLKDIV6, 3, 0)
+DEFINE_BIT(GPT6_CLK_CLK6, 4)
+
+#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h
new file mode 100644
index 0000000000..507814b233
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_v2.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_V2_H
+#define SOC_MEDIATEK_COMMON_TIMER_V2_H
+
+#include <device/mmio.h>
+#include <soc/timer_common.h>
+#include <types.h>
+
+#define GPT_MHZ 13
+
+struct mtk_gpt_regs {
+ u32 reserved1[40];
+ u32 gpt6_con;
+ u32 reserved2;
+ u32 gpt6_cnt_l;
+ u32 reserved3;
+ u32 gpt6_cnt_h;
+};
+
+check_member(mtk_gpt_regs, gpt6_con, 0x00A0);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x00A8);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x00B0);
+
+DEFINE_BIT(GPT6_CON_EN6, 0)
+DEFINE_BIT(GPT6_CON_CLR6, 1)
+DEFINE_BITFIELD(GPT6_CON_MODE6, 6, 5)
+
+#define GPT6_CLOCK_REG(x) x->gpt6_con
+DEFINE_BITFIELD(GPT6_CLK_CLKDIV6, 3, 0)
+DEFINE_BITFIELD(GPT6_CLK_CLK6, 13, 10)
+
+#endif
diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c
index 7b9e424153..5feed3420b 100644
--- a/src/soc/mediatek/common/timer.c
+++ b/src/soc/mediatek/common/timer.c
@@ -35,11 +35,15 @@ void init_timer(void)
timer_prepare();
/* Disable timer and clear the counter */
- clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN);
- setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
+ clrbits32(&mtk_gpt->gpt6_con, GPT6_CON_EN);
+ setbits32(&mtk_gpt->gpt6_con, GPT6_CON_CLR);
/* Set clock source to system clock and set clock divider to 1 */
- write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
+ SET32_BITFIELDS(&GPT6_CLOCK_REG(mtk_gpt),
+ GPT6_CLK_CLK6, GPT6_CLK_CLK6_SYS,
+ GPT6_CLK_CLKDIV6, GPT6_CLK_CLKDIV_DIV1);
/* Set operation mode to FREERUN mode and enable timer */
- write32(&mtk_gpt->gpt6_con, GPT_CON_EN | GPT_MODE_FREERUN);
+ SET32_BITFIELDS(&mtk_gpt->gpt6_con,
+ GPT6_CON_MODE6, GPT6_MODE_FREERUN,
+ GPT6_CON_EN6, GPT6_CON_EN);
}
diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h
new file mode 100644
index 0000000000..da378acb93
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/timer.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8173_TIMER_H
+#define SOC_MEDIATEK_MT8173_TIMER_H
+
+#include <soc/timer_v1.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/timer.h b/src/soc/mediatek/mt8183/include/soc/timer.h
new file mode 100644
index 0000000000..08d9d6238d
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/timer.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8183_TIMER_H
+#define SOC_MEDIATEK_MT8183_TIMER_H
+
+#include <soc/timer_v1.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8192/include/soc/timer.h b/src/soc/mediatek/mt8192/include/soc/timer.h
new file mode 100644
index 0000000000..7703e6a5bb
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/timer.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_TIMER_H
+#define SOC_MEDIATEK_MT8192_TIMER_H
+
+#include <soc/timer_v1.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 3fa1d1993d..302d2ff1ea 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -3,26 +3,26 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
bootblock-y += bootblock.c
bootblock-y += ../common/mmu_operations.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
-bootblock-y += ../common/timer.c
+bootblock-y += ../common/timer.c timer.c
bootblock-y += ../common/uart.c
bootblock-y += ../common/wdt.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
-verstage-y += ../common/timer.c
+verstage-y += ../common/timer.c timer.c
verstage-y += ../common/uart.c
verstage-y += ../common/wdt.c
romstage-y += ../common/cbmem.c
romstage-y += emi.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
-romstage-y += ../common/timer.c
+romstage-y += ../common/timer.c timer.c
romstage-y += ../common/uart.c
romstage-y += ../common/wdt.c
ramstage-y += emi.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += soc.c
-ramstage-y += ../common/timer.c
+ramstage-y += ../common/timer.c timer.c
ramstage-y += ../common/uart.c
ramstage-y += ../common/wdt.c
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index 0f4bb8b450..417e2bd2c2 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -22,6 +22,7 @@ enum {
GPT_BASE = IO_PHYS + 0x00008000,
EINT_BASE = IO_PHYS + 0x0000B000,
APMIXED_BASE = IO_PHYS + 0x0000C000,
+ SYSTIMER_BASE = IO_PHYS + 0x00017000,
PMIF_SPI_BASE = IO_PHYS + 0x00024000,
PMICSPI_MST_BASE = IO_PHYS + 0x00025000,
PMIF_SPMI_BASE = IO_PHYS + 0x00027000,
diff --git a/src/soc/mediatek/mt8195/include/soc/timer.h b/src/soc/mediatek/mt8195/include/soc/timer.h
new file mode 100644
index 0000000000..da073e1b7a
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/timer.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_TIMER_H
+#define SOC_MEDIATEK_MT8195_TIMER_H
+
+#include <soc/timer_v2.h>
+
+enum {
+ TIE_0_EN = 1 << 3,
+ COMP_15_EN = 1 << 10,
+ COMP_20_EN = 1 << 11,
+ COMP_25_EN = 1 << 12,
+
+ COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN,
+
+ COMP_15_MASK = COMP_15_EN,
+ COMP_20_MASK = COMP_20_EN | TIE_0_EN,
+ COMP_25_MASK = COMP_20_EN | COMP_25_EN,
+};
+#endif
diff --git a/src/soc/mediatek/mt8195/timer.c b/src/soc/mediatek/mt8195/timer.c
new file mode 100644
index 0000000000..3fb4be7f2d
--- /dev/null
+++ b/src/soc/mediatek/mt8195/timer.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/timer.h>
+
+void timer_prepare(void)
+{
+ clrbits32((void *)SYSTIMER_BASE, COMP_FEATURE_MASK);
+ setbits32((void *)SYSTIMER_BASE, COMP_25_MASK);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:26:12 +0000