diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 60fb5822cd..6ff2b77608 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,16 +38,7 @@ SECTIONS QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) -#ifdef __PRE_RAM__ - /* - * ipq8064 is different from most other ARM platforms: it loads the - * proprietary DRAM initialization code from CBFS (as opposed to compiling - * it in into rombase). As a result CBFS needs to be used before DRAM is - * availale, which means CBFS cache must be in SRAM, which in turn means - * that PRERAM_CBFS_CACHE description can not be used here. - */ - CBFS_CACHE(0x2A044000, 93K) -#endif + PRERAM_CBFS_CACHE(0x2A044000, 93K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) SRAM_END(0x2A060000) @@ -55,8 +46,6 @@ SECTIONS DRAM_START(0x40000000) RAMSTAGE(0x40640000, 128K) SYMBOL(memlayout_cbmem_top, 0x59F80000) -#ifndef __PRE_RAM__ - CBFS_CACHE(0x59F80000, 384K) -#endif + POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) } |