summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/qualcomm/ipq806x/uart.c136
1 files changed, 69 insertions, 67 deletions
diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c
index 0a19e9a4f2..ffb58c9495 100644
--- a/src/soc/qualcomm/ipq806x/uart.c
+++ b/src/soc/qualcomm/ipq806x/uart.c
@@ -46,8 +46,8 @@
#define FIFO_DATA_SIZE 4
typedef struct {
- unsigned uart_dm_base;
- unsigned uart_gsbi_base;
+ void *uart_dm_base;
+ void *uart_gsbi_base;
unsigned uart_gsbi;
uart_clk_mnd_t mnd_value;
gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
@@ -58,31 +58,31 @@ typedef struct {
* board/qcom/ipq806x_cdp/ipq806x_board_param.h
*/
static const uart_params_t uart_board_param = {
- .uart_dm_base = UART4_DM_BASE,
- .uart_gsbi_base = UART_GSBI4_BASE,
+ .uart_dm_base = (void *)UART4_DM_BASE,
+ .uart_gsbi_base = (void *)UART_GSBI4_BASE,
.uart_gsbi = GSBI_4,
.mnd_value = { 12, 625, 313 },
- .dbg_uart_gpio = {
- {
- .gpio = 10,
- .func = 1,
- .dir = GPIO_OUTPUT,
- .pull = GPIO_NO_PULL,
- .drvstr = GPIO_12MA,
- .enable = GPIO_DISABLE
- },
- {
- .gpio = 11,
- .func = 1,
- .dir = GPIO_INPUT,
- .pull = GPIO_NO_PULL,
- .drvstr = GPIO_12MA,
- .enable = GPIO_DISABLE
- },
- }
+ .dbg_uart_gpio = {
+ {
+ .gpio = 10,
+ .func = 1,
+ .dir = GPIO_OUTPUT,
+ .pull = GPIO_NO_PULL,
+ .drvstr = GPIO_12MA,
+ .enable = GPIO_DISABLE
+ },
+ {
+ .gpio = 11,
+ .func = 1,
+ .dir = GPIO_INPUT,
+ .pull = GPIO_NO_PULL,
+ .drvstr = GPIO_12MA,
+ .enable = GPIO_DISABLE
+ },
+ }
};
-static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base);
+static unsigned int msm_boot_uart_dm_init(void *uart_dm_base);
/* Received data is valid or not */
static int valid_data = 0;
@@ -94,24 +94,24 @@ static unsigned int word = 0;
* msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
* @uart_dm_base: UART controller base address
*/
-static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base)
+static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
{
/* Reset receiver */
- writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX,
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX,
MSM_BOOT_UART_DM_CR(uart_dm_base));
/* Enable receiver */
- writel_i(MSM_BOOT_UART_DM_CR_RX_ENABLE,
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE,
MSM_BOOT_UART_DM_CR(uart_dm_base));
- writel_i(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
MSM_BOOT_UART_DM_DMRX(uart_dm_base));
/* Clear stale event */
- writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
MSM_BOOT_UART_DM_CR(uart_dm_base));
/* Enable stale event */
- writel_i(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
MSM_BOOT_UART_DM_CR(uart_dm_base));
return MSM_BOOT_UART_DM_E_SUCCESS;
@@ -132,7 +132,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
{
static int total_rx_data = 0;
static int rx_data_read = 0;
- unsigned int base = 0;
+ void *base;
uint32_t status_reg;
base = uart_board_param.uart_dm_base;
@@ -140,19 +140,19 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
if (data == NULL)
return MSM_BOOT_UART_DM_E_INVAL;
- status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base));
+ status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
/* Check for DM_RXSTALE for RX transfer to finish */
while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
- status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base));
+ status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
if (!wait)
return MSM_BOOT_UART_DM_E_RX_NOT_READY;
}
/* Check for Overrun error. We'll just reset Error Status */
- if (readl_i(MSM_BOOT_UART_DM_SR(base)) &
+ if (readl(MSM_BOOT_UART_DM_SR(base)) &
MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
- writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
MSM_BOOT_UART_DM_CR(base));
total_rx_data = rx_data_read = 0;
msm_boot_uart_dm_init(base);
@@ -161,10 +161,10 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
if (total_rx_data == 0)
- total_rx_data = readl_i(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
+ total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
/* Data available in FIFO; read a word. */
- *data = readl_i(MSM_BOOT_UART_DM_RF(base, 0));
+ *data = readl(MSM_BOOT_UART_DM_RF(base, 0));
/* WAR for http://prism/CR/548280 */
if (*data == 0) {
@@ -194,35 +194,36 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
void uart_tx_byte(int idx, unsigned char data)
{
- unsigned int base = uart_board_param.uart_dm_base;
+ int num_of_chars = 1;
+ unsigned tx_data = 0;
+ void *base = uart_board_param.uart_dm_base;
/* Wait until transmit FIFO is empty. */
- while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) &
- MSM_BOOT_UART_DM_SR_TXEMT))
- udelay(1);
-
+ while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
+ MSM_BOOT_UART_DM_SR_TXEMT))
+ udelay(1);
/*
* TX FIFO is ready to accept new character(s). First write number of
* characters to be transmitted.
*/
- writel_i(1, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
/* And now write the character(s) */
- writel_i(data, MSM_BOOT_UART_DM_TF(base, 0));
+ writel(tx_data, MSM_BOOT_UART_DM_TF(base, 0));
}
/*
* msm_boot_uart_dm_reset - resets UART controller
* @base: UART controller base address
*/
-static unsigned int msm_boot_uart_dm_reset(unsigned int base)
+static unsigned int msm_boot_uart_dm_reset(void *base)
{
- writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
- writel_i(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
- writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
MSM_BOOT_UART_DM_CR(base));
- writel_i(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
- writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -231,18 +232,18 @@ static unsigned int msm_boot_uart_dm_reset(unsigned int base)
* msm_boot_uart_dm_init - initilaizes UART controller
* @uart_dm_base: UART controller base address
*/
-static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
+static unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
{
/* Configure UART mode registers MR1 and MR2 */
/* Hardware flow control isn't supported */
- writel_i(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
+ writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
- writel_i(MSM_BOOT_UART_DM_8_N_1_MODE,
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE,
MSM_BOOT_UART_DM_MR2(uart_dm_base));
/* Configure Interrupt Mask register IMR */
- writel_i(MSM_BOOT_UART_DM_IMR_ENABLED,
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED,
MSM_BOOT_UART_DM_IMR(uart_dm_base));
/*
@@ -250,25 +251,25 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
* TX watermark value is set to 0 - interrupt is generated when
* FIFO level is less than or equal to 0
*/
- writel_i(MSM_BOOT_UART_DM_TFW_VALUE,
+ writel(MSM_BOOT_UART_DM_TFW_VALUE,
MSM_BOOT_UART_DM_TFWR(uart_dm_base));
/* RX watermark value */
- writel_i(MSM_BOOT_UART_DM_RFW_VALUE,
+ writel(MSM_BOOT_UART_DM_RFW_VALUE,
MSM_BOOT_UART_DM_RFWR(uart_dm_base));
/* Configure Interrupt Programming Register */
/* Set initial Stale timeout value */
- writel_i(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
MSM_BOOT_UART_DM_IPR(uart_dm_base));
/* Configure IRDA if required */
/* Disabling IRDA mode */
- writel_i(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
+ writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
/* Configure hunt character value in HCR register */
/* Keep it in reset state */
- writel_i(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
+ writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
/*
* Configure Rx FIFO base address
@@ -283,10 +284,10 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
/* Enable/Disable Rx/Tx DM interfaces */
/* Data Mover not currently utilized. */
- writel_i(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
+ writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
/* Enable transmitter */
- writel_i(MSM_BOOT_UART_DM_CR_TX_ENABLE,
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE,
MSM_BOOT_UART_DM_CR(uart_dm_base));
/* Initialize Receive Path */
@@ -303,7 +304,8 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
void uart_init(int idx)
{
/* Note int idx isn't used in this driver. */
- unsigned int dm_base, gsbi_base;
+ void *dm_base;
+ void *gsbi_base;
dm_base = uart_board_param.uart_dm_base;
gsbi_base = uart_board_param.uart_gsbi_base;
@@ -311,16 +313,16 @@ void uart_init(int idx)
NO_OF_DBG_UART_GPIOS);
/* Configure the uart clock */
- uart_clock_config(uart_board_param.uart_gsbi,
+ uart_clock_config(uart_board_param.uart_gsbi,
uart_board_param.mnd_value.m_value,
uart_board_param.mnd_value.n_value,
uart_board_param.mnd_value.d_value,
0);
- writel_i(GSBI_PROTOCOL_CODE_I2C_UART <<
+ writel(GSBI_PROTOCOL_CODE_I2C_UART <<
GSBI_CTRL_REG_PROTOCOL_CODE_S,
GSBI_CTRL_REG(gsbi_base));
- writel_i(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
/* Intialize UART_DM */
msm_boot_uart_dm_init(dm_base);
@@ -329,7 +331,7 @@ void uart_init(int idx)
#if 0 /* Not used yet */
uint32_t uartmem_getbaseaddr(void)
{
- return uart_board_param.uart_dm_base;
+ return (uint32_t)uart_board_param.uart_dm_base;
}
#endif
@@ -339,9 +341,9 @@ uint32_t uartmem_getbaseaddr(void)
*/
void uart_tx_flush(int idx)
{
- unsigned int base = uart_board_param.uart_dm_base;
+ void *base = uart_board_param.uart_dm_base;
- while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) &
+ while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
MSM_BOOT_UART_DM_SR_TXEMT))
;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 11:20:29 +0000