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-rw-r--r--src/soc/intel/apollolake/Kconfig13
-rw-r--r--src/soc/intel/apollolake/Makefile.inc1
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspUpd.h37
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h568
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h565
-rw-r--r--src/soc/intel/apollolake/include/soc/iomap.h27
-rw-r--r--src/soc/intel/apollolake/include/soc/romstage.h21
-rw-r--r--src/soc/intel/apollolake/romstage.c155
8 files changed, 1387 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 2f6101582f..e113369917 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -90,4 +90,17 @@ config C_ENV_BOOTBLOCK_SIZE
config X86_TOP4G_BOOTMEDIA_MAP
bool
default n
+
+config ROMSTAGE_ADDR
+ hex
+ default 0xfef2e000
+ help
+ The base address (in CAR) where romstage should be linked
+
+config FSPM_STACK_SIZE
+ hex
+ default 0x40000
+ help
+ The amount of CAR memory FSPM needs. Recommended at least 256KiB
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e27fd27128..81ca688d67 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -17,6 +17,7 @@ bootblock-y += tsc_freq.c
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += placeholders.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
romstage-y += gpio.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += mmap_boot.c
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
new file mode 100644
index 0000000000..da3486df1d
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP_API_H_
+#define _FSP_API_H_
+
+/** FSP UPD Header
+**/
+struct FSP_UPD_HEADER {
+
+/** Offset 0x00 to 0x07 - UPD Region Signature
+ The signature will be
+ "FSPT_UPD" for FSP-T
+ "FSPM_UPD" for FSP-M
+ "FSPS_UPD" for FSP-S
+**/
+ uint64_t Signature;
+
+/** Offset 0x08 - Revision
+**/
+ uint8_t Revision;
+
+/** Offset 0x09 to 0x1F - ReservedUpd
+**/
+ uint8_t ReservedUpd[23];
+} __attribute__((packed));
+
+#endif /* _FSP_API_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
new file mode 100644
index 0000000000..e55b42b72d
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
@@ -0,0 +1,568 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include "FspUpd.h"
+
+
+typedef union {
+ uint32_t PadCnf0;
+ struct {
+ uint32_t GPIOTxState:1; ///< 0 GPIO TX State
+ uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO
+ uint32_t Reserved1:6; ///< 2-7 Reserved, RO
+ uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8]
+ uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc.
+ uint32_t Reserved2:4; ///< 13-16 Reserved, RO
+ uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17]
+ uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO
+ uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion
+ uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT
+ uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge
+ uint32_t Reserved3:1; ///< 27 RO
+ uint32_t RXRAW1:1; ///< 28 Override the RX to 1
+ uint32_t RXPadStSel:1; ///< 29 RX Pad State Select
+ uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config
+ } r;
+} BL_CONF_PAD0;
+
+typedef union {
+ uint32_t PadCnf1;
+ struct {
+ uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO
+ uint32_t Reserved:1; ///< 7 Reserved.
+ uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW
+ uint32_t Term:4; ///< 10-13 Termination,
+ ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu;
+ ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination
+ uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW
+ uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO
+ } r;
+} BL_CONF_PAD1;
+
+struct BL_GPIO_PAD_INIT {
+ BL_CONF_PAD0 PadConfg0;
+ BL_CONF_PAD1 PadConfg1;
+ uint8_t Community;
+ uint16_t MmioAddress;
+ bool HostSw;
+ bool WakeEnabled;
+ wchar_t *PadName;
+} __attribute__((packed));
+
+/** Fsp M Architectural UPD
+**/
+struct FSP_M_ARCH_UPD {
+
+/** Offset 0x0020
+**/
+ uint8_t Revision;
+
+/** Offset 0x0021
+**/
+ uint8_t Reserved[3];
+
+/** Offset 0x0024
+**/
+ void* NvsBufferPtr;
+
+/** Offset 0x0028 - StackBase
+ To hold the stack base.
+**/
+ void* StackBase;
+
+/** Offset 0x002C - StackSize
+ To hold the stack size.
+**/
+ uint32_t StackSize;
+
+/** Offset 0x0030 - BootLoaderTolumSize
+ To pass Bootloader Tolum size.
+**/
+ uint32_t BootLoaderTolumSize;
+
+/** Offset 0x0034 - Bootmode
+ To maintain Bootmode details.
+**/
+ uint32_t Bootmode;
+
+/** Offset 0x0038
+**/
+ uint8_t ReservedFspmArchUpd[8];
+} __attribute__((packed));
+
+/** Fsp M Configuration
+**/
+struct FSP_M_CONFIG {
+
+/** Offset 0x0040 - Debug Serial Port Base
+ Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'.
+**/
+ uint32_t SerialDebugPortAddress;
+
+/** Offset 0x0044 - Debug Serial Port Type
+ 16550 compatible debug serial port resource type. NONE means no serial port support.
+ 0:NONE, 1:I/O, 2:MMIO
+**/
+ uint8_t SerialDebugPortType;
+
+/** Offset 0x0045 - Serial Port Debug Device
+ Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored.
+ 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
+**/
+ uint8_t SerialDebugPortDevice;
+
+/** Offset 0x0046 - Debug Serial Port Stride Size
+ Debug serial port register map stride size in bytes.
+ 0:1, 2:4
+**/
+ uint8_t SerialDebugPortStrideSize;
+
+/** Offset 0x0047 - Memory Fast Boot
+ Enable/Disable MRC fast boot support.
+ $EN_DIS
+**/
+ uint8_t MrcFastBoot;
+
+/** Offset 0x0048 - Integrated Graphics Device
+ Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD.
+ $EN_DIS
+**/
+ uint8_t Igd;
+
+/** Offset 0x0049 - DVMT Pre-Allocated
+ Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.
+ 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB
+**/
+ uint8_t IgdDvmt50PreAlloc;
+
+/** Offset 0x004A - Aperture Size
+ Select the Aperture Size used by the Internal Graphics Device.
+ 0x1:128 MB, 0x2:256 MB, 0x3:512 MB
+**/
+ uint8_t IgdApertureSize;
+
+/** Offset 0x004B - GTT Size
+ Select the GTT Size used by the Internal Graphics Device.
+ 0x1:2 MB, 0x2:4 MB, 0x3:8 MB
+**/
+ uint8_t GttSize;
+
+/** Offset 0x004C - Primary Display
+ Select which of IGD/PCI Graphics device should be Primary Display.
+ 0x0:AUTO, 0x2:IGD, 0x3:PCI
+**/
+ uint8_t PrimaryVideoAdaptor;
+
+/** Offset 0x004D - Package
+ NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used.
+ 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD
+**/
+ uint8_t Package;
+
+/** Offset 0x004E - Profile
+ Profile list
+ 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
+**/
+ uint8_t Profile;
+
+/** Offset 0x004F - MemoryDown
+ Memory Down.
+ 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
+**/
+ uint8_t MemoryDown;
+
+/** Offset 0x0050 - DDR3LPageSize
+ NOTE: Only for memory down or downgrade DDR3L frequency.
+ 0x1:1KB, 0x2:2KB
+**/
+ uint8_t DDR3LPageSize;
+
+/** Offset 0x0051 - DDR3LASR
+ NOTE: Only for memory down.
+ 0x0:Not Supported, 0x1:Supported
+**/
+ uint8_t DDR3LASR;
+
+/** Offset 0x0052 - ScramblerSupport
+ Scrambler Support.
+ $EN_DIS
+**/
+ uint8_t ScramblerSupport;
+
+/** Offset 0x0053 - ChannelHashMask
+ Channel Hash Mask.
+**/
+ uint16_t ChannelHashMask;
+
+/** Offset 0x0055 - SliceHashMask
+ Slice Hash Mask.
+**/
+ uint16_t SliceHashMask;
+
+/** Offset 0x0057 - InterleavedMode
+ Interleaved Mode.
+ $EN_DIS
+**/
+ uint8_t InterleavedMode;
+
+/** Offset 0x0058 - ChannelsSlicesEnable
+ Channels Slices Enable.
+ $EN_DIS
+**/
+ uint8_t ChannelsSlicesEnable;
+
+/** Offset 0x0059 - MinRefRate2xEnable
+ Provided as a means to defend against Row-Hammer attacks.
+ $EN_DIS
+**/
+ uint8_t MinRefRate2xEnable;
+
+/** Offset 0x005A - DualRankSupportEnable
+ Dual Rank Support Enable.
+ $EN_DIS
+**/
+ uint8_t DualRankSupportEnable;
+
+/** Offset 0x005B - RmtMode
+ Rank Margin Tool Mode.
+ $EN_DIS
+**/
+ uint8_t RmtMode;
+
+/** Offset 0x005C - MemorySizeLimit
+ Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB.
+**/
+ uint16_t MemorySizeLimit;
+
+/** Offset 0x005E - LowMemoryMaxValue
+ Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB.
+**/
+ uint16_t LowMemoryMaxValue;
+
+/** Offset 0x0060 - DisableFastBoot
+ 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory.
+ $EN_DIS
+**/
+ uint8_t DisableFastBoot;
+
+/** Offset 0x0061 - HighMemoryMaxValue
+ High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB.
+**/
+ uint16_t HighMemoryMaxValue;
+
+/** Offset 0x0063 - DIMM0SPDAddress
+ DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown.
+**/
+ uint8_t DIMM0SPDAddress;
+
+/** Offset 0x0064 - DIMM1SPDAddress
+ DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown.
+**/
+ uint8_t DIMM1SPDAddress;
+
+/** Offset 0x0065 - Ch0_RankEnable
+ NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank.
+**/
+ uint8_t Ch0_RankEnable;
+
+/** Offset 0x0066 - Ch0_DeviceWidth
+ NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1.
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch0_DeviceWidth;
+
+/** Offset 0x0067 - Ch0_DramDensity
+ NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1.
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch0_DramDensity;
+
+/** Offset 0x0068 - Ch0_Option
+ [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B).
+**/
+ uint8_t Ch0_Option;
+
+/** Offset 0x0069 - Ch0_OdtConfig
+ [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n.
+**/
+ uint8_t Ch0_OdtConfig;
+
+/** Offset 0x006A - Ch0_TristateClk1
+ [0] Parameter used to determine whether to tristate CLK1.\n Boolean value.
+**/
+ uint8_t Ch0_TristateClk1;
+
+/** Offset 0x006B - Ch0_Mode2N
+ [0] 2N Mode.\n Boolean value.
+**/
+ uint8_t Ch0_Mode2N;
+
+/** Offset 0x006C - Ch0_OdtLevels
+ [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B).
+**/
+ uint8_t Ch0_OdtLevels;
+
+/** Offset 0x006D - Ch1_RankEnable
+ NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank.
+**/
+ uint8_t Ch1_RankEnable;
+
+/** Offset 0x006E - Ch1_DeviceWidth
+ NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1.
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch1_DeviceWidth;
+
+/** Offset 0x006F - Ch1_DramDensity
+ NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1.
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch1_DramDensity;
+
+/** Offset 0x0070 - Ch1_Option
+ [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B).
+**/
+ uint8_t Ch1_Option;
+
+/** Offset 0x0071 - Ch1_OdtConfig
+ [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n.
+**/
+ uint8_t Ch1_OdtConfig;
+
+/** Offset 0x0072 - Ch1_TristateClk1
+ [0] Parameter used to determine whether to tristate CLK1.\nBoolean value.
+**/
+ uint8_t Ch1_TristateClk1;
+
+/** Offset 0x0073 - Ch1_Mode2N
+ [0] 2N Mode.\nBoolean value.
+**/
+ uint8_t Ch1_Mode2N;
+
+/** Offset 0x0074 - Ch1_OdtLevels
+ [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW.
+**/
+ uint8_t Ch1_OdtLevels;
+
+/** Offset 0x0075 - Ch2_RankEnable
+ NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank.
+**/
+ uint8_t Ch2_RankEnable;
+
+/** Offset 0x0076 - Ch2_DeviceWidth
+ NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1.
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch2_DeviceWidth;
+
+/** Offset 0x0077 - Ch2_DramDensity
+ NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1.
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch2_DramDensity;
+
+/** Offset 0x0078 - Ch2_Option
+ [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B).
+**/
+ uint8_t Ch2_Option;
+
+/** Offset 0x0079 - Ch2_OdtConfig
+ [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n.
+**/
+ uint8_t Ch2_OdtConfig;
+
+/** Offset 0x007A - Ch2_TristateClk1
+ [0] Parameter used to determine whether to tristate CLK1.\nBoolean value.
+**/
+ uint8_t Ch2_TristateClk1;
+
+/** Offset 0x007B - Ch2_Mode2N
+ [0] 2N Mode.\nBoolean value.
+**/
+ uint8_t Ch2_Mode2N;
+
+/** Offset 0x007C - Ch2_OdtLevels
+ [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW.
+**/
+ uint8_t Ch2_OdtLevels;
+
+/** Offset 0x007D - Ch3_RankEnable
+ NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank.
+**/
+ uint8_t Ch3_RankEnable;
+
+/** Offset 0x007E - Ch3_DeviceWidth
+ NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1.
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch3_DeviceWidth;
+
+/** Offset 0x007F - Ch3_DramDensity
+ NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1.
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch3_DramDensity;
+
+/** Offset 0x0080 - Ch3_Option
+ [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B).
+**/
+ uint8_t Ch3_Option;
+
+/** Offset 0x0081 - Ch3_OdtConfig
+ [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n.
+**/
+ uint8_t Ch3_OdtConfig;
+
+/** Offset 0x0082 - Ch3_TristateClk1
+ [0] Parameter used to determine whether to tristate CLK1.\nBoolean value.
+**/
+ uint8_t Ch3_TristateClk1;
+
+/** Offset 0x0083 - Ch3_Mode2N
+ [0] 2N Mode.\nBoolean value.
+**/
+ uint8_t Ch3_Mode2N;
+
+/** Offset 0x0084 - Ch3_OdtLevels
+ [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW.
+**/
+ uint8_t Ch3_OdtLevels;
+
+/** Offset 0x0085 - RmtCheckRun
+ [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW.
+**/
+ uint8_t RmtCheckRun;
+
+/** Offset 0x0086 - Ch0_Bit_swizzling
+ Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch0_Bit_swizzling[32];
+
+/** Offset 0x00A6 - Ch1_Bit_swizzling
+ Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch1_Bit_swizzling[32];
+
+/** Offset 0x00C6 - Ch2_Bit_swizzling
+ Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch2_Bit_swizzling[32];
+
+/** Offset 0x00E6 - Ch3_Bit_swizzling
+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch3_Bit_swizzling[32];
+
+/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold
+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint16_t RmtMarginCheckScaleHighThreshold;
+
+/** Offset 0x0108 - MsgLevelMask
+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint32_t MsgLevelMask;
+
+/** Offset 0x010C - FIT Table Pointer
+ FIT table pointer.
+**/
+ uint32_t FitTablePtr;
+
+/** Offset 0x0110 - GPIO Table Pointer
+ GPIO table pointer to a BL_GPIO_PAD_INIT structure.
+**/
+ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr;
+
+/** Offset 0x0114
+**/
+ uint8_t ReservedFspmUpd[60];
+} __attribute__((packed));
+
+/** Fsp M Test Configuration
+**/
+struct FSP_M_TEST_CONFIG {
+
+/** Offset 0x0150
+**/
+ uint32_t Signature;
+
+/** Offset 0x0154
+**/
+ uint8_t ReservedFspmTestUpd[28];
+} __attribute__((packed));
+
+/** Fsp M Restricted Configuration
+**/
+struct FSP_M_RESTRICTED_CONFIG {
+
+/** Offset 0x0170
+**/
+ uint32_t Signature;
+
+/** Offset 0x0174
+**/
+ uint8_t ReservedFspmRestrictedUpd[138];
+} __attribute__((packed));
+
+#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */
+
+struct FSPM_UPD {
+
+/** Offset 0x0000
+**/
+ struct FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ struct FSP_M_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ struct FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0150
+**/
+ struct FSP_M_TEST_CONFIG FspmTestConfig;
+
+/** Offset 0x0170
+**/
+ struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
+
+/** Offset 0x01FE
+**/
+ uint16_t UpdTerminator;
+} __attribute__((packed));
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
new file mode 100644
index 0000000000..f2f867b64d
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
@@ -0,0 +1,565 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include "FspUpd.h"
+
+
+/** Fsp S Configuration
+**/
+struct FSP_S_CONFIG {
+
+/** Offset 0x0020 - ActiveProcessorCores
+ Number of active cores.
+**/
+ uint8_t ActiveProcessorCores;
+
+/** Offset 0x0021 - Disable Core1
+ Disable/Enable Core1.
+ $EN_DIS
+**/
+ uint8_t DisableCore1;
+
+/** Offset 0x0022 - Disable Core2
+ Disable/Enable Core2.
+ $EN_DIS
+**/
+ uint8_t DisableCore2;
+
+/** Offset 0x0023 - Disable Core3
+ Disable/Enable Core3.
+ $EN_DIS
+**/
+ uint8_t DisableCore3;
+
+/** Offset 0x0024 - VMX Enable
+ Enable or Disable VMX.
+ $EN_DIS
+**/
+ uint8_t VmxEnable;
+
+/** Offset 0x0025 - Memory region allocation for Processor Trace
+ Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable.
+**/
+ uint8_t ProcTraceMemSize;
+
+/** Offset 0x0026 - Enable Processor Trace
+ Enable or Disable Processor Trace feature.
+ $EN_DIS
+**/
+ uint8_t ProcTraceEnable;
+
+/** Offset 0x0027 - Eist
+ Enable or Disable Intel SpeedStep Technology.
+ $EN_DIS
+**/
+ uint8_t Eist;
+
+/** Offset 0x0028 - Boot PState
+ Boot PState with HFM or LFM. 0: HFM; 1: LFM.
+**/
+ uint8_t BootPState;
+
+/** Offset 0x0029 - CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t EnableCx;
+
+/** Offset 0x002A - Enhanced C-states
+ Enable or Disable Enhanced C-states. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t C1e;
+
+/** Offset 0x002B - Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t BiProcHot;
+
+/** Offset 0x002C - Max Pkg Cstate
+ Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto.
+**/
+ uint8_t PkgCStateLimit;
+
+/** Offset 0x002D
+**/
+ uint8_t UnusedUpdSpace0;
+
+/** Offset 0x002E - C-State auto-demotion
+ C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3.
+**/
+ uint8_t CStateAutoDemotion;
+
+/** Offset 0x002F - C-State un-demotion
+ C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion.
+**/
+ uint8_t CStateUnDemotion;
+
+/** Offset 0x0030 - Max Core C-State
+ Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx.
+**/
+ uint8_t MaxCoreCState;
+
+/** Offset 0x0031 - Package C-State Demotion
+ Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t PkgCStateDemotion;
+
+/** Offset 0x0032 - Package C-State Un-demotion
+ Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t PkgCStateUnDemotion;
+
+/** Offset 0x0033 - Turbo Mode
+ Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable.
+ $EN_DIS
+**/
+ uint8_t TurboMode;
+
+/** Offset 0x0034
+**/
+ uint8_t UnusedUpdSpace1[12];
+
+/** Offset 0x0040 - HD-Audio I/O Buffer Ownership
+ Set HD-Audio I/O Buffer Ownership.
+ 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
+**/
+ uint8_t HdAudioIoBufferOwnership;
+
+/** Offset 0x0041
+**/
+ uint8_t UnusedUpdSpace2[5];
+
+/** Offset 0x0046 - Enable SD controller
+ Enable/disable SD Card controller.
+ $EN_DIS
+**/
+ uint8_t SdcardEnabled;
+
+/** Offset 0x0047 - Enable SDIO controller
+ Enable/disable SDIO controller.
+ $EN_DIS
+**/
+ uint8_t SdioEnabled;
+
+/** Offset 0x0048 - Enable eMMC controller
+ Enable/disable eMMC controller.
+ $EN_DIS
+**/
+ uint8_t eMMCEnabled;
+
+/** Offset 0x0049 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ uint8_t EnableSata;
+
+/** Offset 0x004A - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ uint8_t SataMode;
+
+/** Offset 0x004B - Aggressive SATA LPM Support
+ Enable SOC to aggressively enter link power state for SATA.
+ $EN_DIS
+**/
+ uint8_t SataSalpSupport;
+
+/** Offset 0x004C - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t SataPortsEnable[2];
+
+/** Offset 0x004E - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t SataPortsDevSlp[2];
+
+/** Offset 0x0050 - Enable PCIE RP
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
+**/
+ uint8_t PcieRootPortEn[6];
+
+/** Offset 0x0056 - Configure CLKREQ Number
+ Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
+**/
+ uint8_t PcieRpClkReqNumber[6];
+
+/** Offset 0x005C
+**/
+ uint8_t UnusedUpdSpace3[16];
+
+/** Offset 0x006C - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t PortUsb20Enable[8];
+
+/** Offset 0x0074 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t PortUsb30Enable[6];
+
+/** Offset 0x007A - Enable XHCI SSIC ports
+ Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1.
+**/
+ uint8_t SsicPortEnable[2];
+
+/** Offset 0x007C - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ uint8_t SmbusEnable;
+
+/** Offset 0x007D - SC HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ uint8_t HdaVerbTableEntryNum;
+
+/** Offset 0x007E - SC HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ uint32_t HdaVerbTablePtr;
+
+/** Offset 0x0082
+**/
+ uint8_t UnusedUpdSpace4[14];
+
+/** Offset 0x0090 - Enable/Disable P2SB device hidden.
+ Enable/Disable P2SB device hidden.
+ $EN_DIS
+**/
+ uint8_t HideP2sb;
+
+/** Offset 0x0091 - Ufs Enable/Disable
+ Enable/Disable Ufs.
+ $EN_DIS
+**/
+ uint8_t UfsEnabled;
+
+/** Offset 0x0092 - IPU Enable/Disable
+ Enable/Disable IPU Device.
+ $EN_DIS
+**/
+ uint8_t IpuEn;
+
+/** Offset 0x0093 - IMGU ACPI mode selection
+ 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device
+ 0:Disable, 1:IGFX Child device, 2:ACPI device
+**/
+ uint8_t IpuAcpiMode;
+
+/** Offset 0x0094 - ResetSelect
+ ResetSelect. 0x6:warm reset; 0xE:cold reset
+**/
+ uint8_t ResetSelect;
+
+/** Offset 0x0095 - CRIDSettings
+ PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3
+**/
+ uint8_t CRIDSettings;
+
+/** Offset 0x0096 - Enable HPET
+ Enable/disable HPET.
+ $EN_DIS
+**/
+ uint8_t Hpet;
+
+/** Offset 0x0097 - Enable PCIE Clock Gating
+ Enable/disable PCIE Clock Gating.0:Enable;1:Disable
+ $EN_DIS
+**/
+ uint8_t PcieClockGatingDisabled;
+
+/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode
+ Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t PcieRootPort8xhDecode;
+
+/** Offset 0x0099 - PCIE 8xh Decode Port Index
+ PCIE 8xh Decode Port Index.
+**/
+ uint8_t Pcie8xhDecodePortIndex;
+
+/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write
+ Enable/disable PCIE root port peer memory write.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t PcieRootPortPeerMemoryWriteEnable;
+
+/** Offset 0x009B - Enable SC Gaussian Mixture Models
+ Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t Gmm;
+
+/** Offset 0x009C - GttMmAdr
+ GttMmAdr structure for initialization.
+**/
+ uint32_t GttMmAdr;
+
+/** Offset 0x00A0
+**/
+ uint8_t UnusedUpdSpace5[96];
+
+/** Offset 0x0100 - Enable S0ix
+ Enable/disable S0ix.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t S0ix;
+
+/** Offset 0x0101 - GmAdr
+ GmAdr structure for initialization.
+**/
+ uint32_t GmAdr;
+
+/** Offset 0x0105 - Enable ForceWake
+ Enable/disable ForceWake Models.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t ForceWake;
+
+/** Offset 0x0106 - Enable PavpLock
+ Enable/disable PavpLock.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t PavpLock;
+
+/** Offset 0x0107 - Enable GraphicsFreqModify
+ Enable/disable GraphicsFreqModify.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t GraphicsFreqModify;
+
+/** Offset 0x0108 - Enable GraphicsFreqReq
+ Enable/disable GraphicsFreqReq.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t GraphicsFreqReq;
+
+/** Offset 0x0109 - Enable GraphicsVideoFreq
+ Enable/disable GraphicsVideoFreq.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t GraphicsVideoFreq;
+
+/** Offset 0x010A - Enable PmLock
+ Enable/disable PmLock.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t PmLock;
+
+/** Offset 0x010B
+**/
+ uint8_t UnusedUpdSpace6[5];
+
+/** Offset 0x0110 - Enable DopClockGating
+ Enable/disable DopClockGating.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t DopClockGating;
+
+/** Offset 0x0111 - Enable UnsolicitedAttackOverride
+ Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t UnsolicitedAttackOverride;
+
+/** Offset 0x0112 - Enable WOPCMSupport
+ Enable/disable WOPCMSupport.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t WOPCMSupport;
+
+/** Offset 0x0113 - Enable WOPCMSize
+ Enable/disable WOPCMSize.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t WOPCMSize;
+
+/** Offset 0x0114 - Enable PowerGating
+ Enable/disable PowerGating.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t PowerGating;
+
+/** Offset 0x0115 - Enable UnitLevelClockGating
+ Enable/disable UnitLevelClockGating.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t UnitLevelClockGating;
+
+/** Offset 0x0116 - Enable FastBoot
+ Enable/disable FastBoot.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t FastBoot;
+
+/** Offset 0x0117 - Enable DynSR
+ Enable/disable DynSR.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t DynSR;
+
+/** Offset 0x0118 - Enable SaIpuEnable
+ Enable/disable SaIpuEnable.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t SaIpuEnable;
+
+/** Offset 0x0119 - Enable VtdEnable
+ Enable/disable VtdEnable.0:Disable;1:Enable
+ $EN_DIS
+**/
+ uint8_t VtdEnable;
+
+/** Offset 0x011A - BMP Logo Data Size
+ BMP logo data buffer size.
+**/
+ uint32_t LogoSize;
+
+/** Offset 0x011E - BMP Logo Data Pointer
+ BMP logo data pointer to a BMP format buffer.
+**/
+ uint32_t LogoPtr;
+
+/** Offset 0x0122 - Graphics Configuration Data Pointer
+ Graphics configuration data used for initialization.
+**/
+ uint32_t GraphicsConfigPtr;
+
+/** Offset 0x0126 - GT PM Support
+ Enable/Disable GT power management support.
+ $EN_DIS
+**/
+ uint8_t PmSupport;
+
+/** Offset 0x0127 - RC6(Render Standby)
+ Enable/Disable render standby support.
+ $EN_DIS
+**/
+ uint8_t EnableRenderStandby;
+
+/** Offset 0x0128 - PAVP Enable
+ Enable/Disable Protected Audio Visual Path (PAVP).
+ $EN_DIS
+**/
+ uint8_t PavpEnable;
+
+/** Offset 0x0129 - PAVP PR3
+ Enable/Disable PAVP PR3
+ $EN_DIS
+**/
+ uint8_t PavpPr3;
+
+/** Offset 0x012A - CdClock Frequency selection
+ 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz
+ 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
+**/
+ uint8_t CdClock;
+
+/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit
+ Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit
+ $EN_DIS
+**/
+ uint8_t PeiGraphicsPeimInit;
+
+/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting
+ Enable/Disable Timer 8254 Clock
+ $EN_DIS
+**/
+ uint8_t Timer8254ClkSetting;
+
+/** Offset 0x012D
+**/
+ uint8_t ReservedFspsUpd[211];
+} __attribute__((packed));
+
+/** Fsp S Test Configuration
+**/
+struct FSP_S_TEST_CONFIG {
+
+/** Offset 0x0200
+**/
+ uint32_t Signature;
+
+/** Offset 0x0204
+**/
+ uint8_t ReservedFspsTestUpd[12];
+} __attribute__((packed));
+
+/** Fsp S Restricted Configuration
+**/
+struct FSP_S_RESTRICTED_CONFIG {
+
+/** Offset 0x0210
+**/
+ uint32_t Signature;
+
+/** Offset 0x0214
+**/
+ uint8_t ReservedFspsRestrictedUpd[12];
+} __attribute__((packed));
+
+#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */
+
+struct FSPS_UPD {
+
+/** Offset 0x0000
+**/
+ struct FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ struct FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0200
+**/
+ struct FSP_S_TEST_CONFIG FspsTestConfig;
+
+/** Offset 0x0210
+**/
+ struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
+
+/** Offset 0x0220
+**/
+ uint16_t UpdTerminator;
+} __attribute__((packed));
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
new file mode 100644
index 0000000000..fb68fbc231
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_IOMAP_H_
+#define _SOC_APOLLOLAKE_IOMAP_H_
+
+#define P2SB_BAR CONFIG_IOSF_BASE_ADDRESS
+#define MCH_BASE_ADDR 0xfed10000
+#define MCH_BASE_SIZE (32 * KiB)
+
+#define ACPI_PMIO_BASE 0x400
+#define R_ACPI_PM1_TMR 0x8
+
+/* Accesses to these BARs are hardcoded in FSP */
+#define PMC_BAR0 0xfe042000
+#define PMC_BAR1 0xfe044000
+
+#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h
new file mode 100644
index 0000000000..9d57d7bdd5
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/romstage.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_
+#define _SOC_APOLLOLAKE_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+
+#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
new file mode 100644
index 0000000000..499417e2ec
--- /dev/null
+++ b/src/soc/intel/apollolake/romstage.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/symbols.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <device/resource.h>
+#include <string.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/northbridge.h>
+#include <soc/romstage.h>
+#include <soc/uart.h>
+
+#define FIT_POINTER (0x100000000ULL - 0x40)
+
+/*
+ * Enables several BARs and devices which are needed for memory init
+ * - MCH_BASE_ADDR is needed in order to talk to the memory controller
+ * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded)
+ * Once raminit is done, we can safely let the allocator re-assign them
+ * - HPET is enabled because FSP wants to store a pointer to global data in the
+ * HPET comparator register
+ */
+static void soc_early_romstage_init(void)
+{
+ device_t pmc = PMC_DEV;
+
+ /* Set MCH base address and enable bit */
+ pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
+
+ /* Set PMC base address */
+ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
+ pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
+ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
+ pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
+
+ /* PMIO BAR4 was already set earlier, hence the COMMAND_IO below */
+ pci_write_config32(pmc, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+
+ /* Enable decoding for HPET. Needed for FSP global pointer storage */
+ pci_write_config32(P2SB_DEV, 0x60, 1<<7);
+}
+
+static void disable_watchdog(void)
+{
+ uint32_t reg;
+ device_t dev = PMC_DEV;
+
+ /* Open up an IO window */
+ pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
+ pci_write_config32(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ /* Stop TCO timer */
+ reg = inl(ACPI_PMIO_BASE + 0x68);
+ reg |= 1 << 11;
+ outl(reg, ACPI_PMIO_BASE + 0x68);
+}
+
+
+asmlinkage void car_stage_entry(void)
+{
+ void *hob_list_ptr;
+ struct resource fsp_mem;
+ struct range_entry reg_car;
+
+ printk(BIOS_DEBUG, "Starting romstage...\n");
+
+ disable_watchdog();
+
+ soc_early_romstage_init();
+
+ /* Make sure the blob does not override our data in CAR */
+ memset(&reg_car, 0, sizeof(reg_car));
+ reg_car.begin = (uintptr_t) _car_relocatable_data_end;
+ reg_car.end = (uintptr_t) _car_region_end;
+
+ if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) {
+ die("FSP memory init failed. Giving up.");
+ }
+
+ fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
+
+ /* initialize cbmem by adding FSP reserved memory first thing */
+ cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_mem.size);
+
+ /* make sure FSP memory is reserved in cbmem */
+ if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
+ die("Failed to accommodate FSP reserved memory request");
+
+ /* Now that CBMEM is up, save the list so ramstage can use it */
+ fsp_save_hob_list(hob_list_ptr);
+
+ run_ramstage();
+}
+
+static void fill_console_params(struct FSPM_UPD *mupd)
+{
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE;
+ /* use MMIO port type */
+ mupd->FspmConfig.SerialDebugPortType = 2;
+ /* use 4 byte register stride */
+ mupd->FspmConfig.SerialDebugPortStrideSize = 2;
+ /* used only for port type set to external */
+ mupd->FspmConfig.SerialDebugPortAddress = 0;
+ } else {
+ mupd->FspmConfig.SerialDebugPortType = 0;
+ }
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
+{
+ fill_console_params(mupd);
+ mainboard_memory_init_params(mupd);
+
+ /* Do NOT let FSP do any GPIO pad configuration */
+ mupd->FspmConfig.GpioPadInitTablePtr = NULL;
+ /*
+ * At FIT_POINTER there is an address that points to FIT. Even though it
+ * is technically 64bit value we know only 32bit address is used.
+ */
+ mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER);
+ /* Reserve enough memory under TOLUD to save CBMEM header */
+ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
+ /* Let FSPM use memory right at the bottom of CAR */
+ /* TODO: Add checks to see if we collide with other areas */
+ mupd->FspmArchUpd.StackBase = _car_region_end - CONFIG_FSPM_STACK_SIZE;
+ mupd->FspmArchUpd.StackSize = CONFIG_FSPM_STACK_SIZE;
+}
+
+__attribute__ ((weak))
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}