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-rw-r--r--src/soc/intel/cannonlake/chip.h10
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2ebe017fbd..9c7c17147e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -136,9 +136,19 @@ struct soc_intel_cannonlake_config {
Sata_AHCI,
Sata_RAID,
} SataMode;
+
+ /* SATA devslp pad reset configuration */
+ enum {
+ SataDevSlpResumeReset = 1,
+ SataDevSlpHostDeepReset = 3,
+ SataDevSlpPlatformReset = 5,
+ SataDevSlpDswReset = 7
+ } SataDevSlpRstConfig;
+
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
+ uint8_t SataPortsDevSlpResetConfig[8];
/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 4038335787..f48a626be9 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -186,6 +186,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
+#if CONFIG(SOC_INTEL_COMETLAKE)
+ memcpy(params->SataPortsDevSlpResetConfig,
+ config->SataPortsDevSlpResetConfig,
+ sizeof(params->SataPortsDevSlpResetConfig));
+#endif
}
/* Lan */