diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/gpio.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 14 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio_defs.h | 5 |
3 files changed, 27 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index a7d88326d1..78495c6467 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -305,9 +305,8 @@ static void gpio_configure_pad(const struct pad_config *cfg) { uint32_t *dw_regs; uint32_t reg; - uint32_t termination; uint32_t dw0; - const uint32_t termination_mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + uint32_t mask; dw_regs = gpio_dw_regs(cfg->pad); @@ -318,10 +317,16 @@ static void gpio_configure_pad(const struct pad_config *cfg) write32(&dw_regs[0], dw0); reg = read32(&dw_regs[1]); - reg &= ~termination_mask; - termination = cfg->attrs; - termination &= termination_mask; - reg |= termination; + + /* Apply termination field */ + mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + reg &= ~mask; + reg |= cfg->attrs & mask; + + /* Apply voltage tolerance field */ + mask = PAD_TOL_MASK << PAD_TOL_SHIFT; + reg &= ~mask; + reg |= cfg->attrs & mask; write32(&dw_regs[1], reg); gpio_handle_pad_mode(cfg); @@ -329,7 +334,7 @@ static void gpio_configure_pad(const struct pad_config *cfg) if ((dw0 & PAD_FIELD(GPIROUTSMI, MASK)) == PAD_FIELD(GPIROUTSMI, YES)) gpi_enable_smi(cfg->pad); - if(gpio_debug) + if (gpio_debug) printk(BIOS_DEBUG, "Write Pad: Base(%p) - conf0 = %x conf1= %x pad # = %d\n", &dw_regs[0], dw0, reg, cfg->pad); diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index f2246e9116..6733889d1a 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) +/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */ +#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \ + NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8)) + /* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. */ #define PAD_CFG_NC(pad_) \ @@ -149,9 +155,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) /* - * The 'attrs' field carries the termination in bits 13:10 to match up with - * thd DW1 pad configuration register. Additionally, other attributes can - * be applied such as the ones below. Bit allocation matters. + * The 'attrs' field carries the termination in bits 13:10 and tolerance in bit + * 25 to match up with thd DW1 pad configuration register. Additionally, other + * attributes can be applied such as the ones below. Bit allocation matters. */ #define HOSTSW_SHIFT 0 #define HOSTSW_MASK 1 @@ -160,7 +166,7 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); struct pad_config { uint16_t pad; - uint16_t attrs; + uint32_t attrs; uint32_t dw0; }; diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 6f9c11134b..4008dfe31d 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -495,6 +495,11 @@ #define PAD_TERM_20K_PU 12 #define PAD_TERM_667_PU 13 #define PAD_TERM_NATIVE 15 + /* TOL - voltage tolerance */ +#define PAD_TOL_SHIFT 25 +#define PAD_TOL_MASK 0x1 +#define PAD_TOL_3V3 0 /* 3.3V default */ +#define PAD_TOL_1V8 1 /* 1.8V tolerant */ #define GPI_GPE_STS_OFFSET 0x140 #define GPI_GPE_EN_OFFSET 0x160 |