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-rw-r--r--src/soc/cavium/cn81xx/cpu.c2
-rw-r--r--src/soc/cavium/cn81xx/include/soc/cpu.h5
-rw-r--r--src/soc/cavium/cn81xx/mmu.c2
-rw-r--r--src/soc/cavium/common/bootblock.c2
-rw-r--r--src/soc/imgtec/pistachio/bootblock.c6
-rw-r--r--src/soc/mediatek/common/include/soc/mmu_operations.h5
-rw-r--r--src/soc/mediatek/common/mmu_operations.c8
-rw-r--r--src/soc/mediatek/mt8173/flash_controller.c4
-rw-r--r--src/soc/mediatek/mt8173/include/soc/symbols.h4
-rw-r--r--src/soc/mediatek/mt8173/mmu_operations.c3
-rw-r--r--src/soc/nvidia/tegra124/verstage.c3
-rw-r--r--src/soc/nvidia/tegra210/mmu_operations.c6
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/symbols.h15
-rw-r--r--src/soc/qualcomm/sdm845/mmu.c6
-rw-r--r--src/soc/qualcomm/sdm845/soc.c2
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c2
-rw-r--r--src/soc/rockchip/rk3288/soc.c2
-rw-r--r--src/soc/rockchip/rk3399/decompressor.c2
-rw-r--r--src/soc/rockchip/rk3399/include/soc/symbols.h9
-rw-r--r--src/soc/rockchip/rk3399/soc.c6
-rw-r--r--src/soc/samsung/exynos5250/alternate_cbfs.c4
-rw-r--r--src/soc/samsung/exynos5250/spi.c2
-rw-r--r--src/soc/samsung/exynos5420/alternate_cbfs.c4
-rw-r--r--src/soc/samsung/exynos5420/spi.c2
24 files changed, 48 insertions, 58 deletions
diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c
index 9504868dff..b655d8a0ed 100644
--- a/src/soc/cavium/cn81xx/cpu.c
+++ b/src/soc/cavium/cn81xx/cpu.c
@@ -81,7 +81,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id))
return 1;
/* Check stack here, instead of in cpu_secondary.S */
- if ((CONFIG_STACK_SIZE * cpu) > _stack_sec_size)
+ if ((CONFIG_STACK_SIZE * cpu) > REGION_SIZE(stack_sec))
return 1;
/* Write the address of the main entry point */
diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h
index 1c6a30dda9..7d3647bda0 100644
--- a/src/soc/cavium/cn81xx/include/soc/cpu.h
+++ b/src/soc/cavium/cn81xx/include/soc/cpu.h
@@ -18,6 +18,7 @@
#define __SOC_CAVIUM_CN81XX_CPU_H__
#include <stdint.h>
+#include <symbols.h>
/**
* Number of the Core on which the program is currently running.
@@ -70,8 +71,6 @@ void secondary_cpu_init(size_t core_id);
/* Symbols in memlayout.ld */
-extern u8 _stack_sec[];
-extern u8 _estack_sec[];
-#define _stack_sec_size (_estack_sec - _stack_sec)
+DECLARE_REGION(stack_sec)
#endif /* __SOC_CAVIUM_CN81XX_CPU_H__ */
diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c
index d6e7ac5ee1..17b43e77ee 100644
--- a/src/soc/cavium/cn81xx/mmu.c
+++ b/src/soc/cavium/cn81xx/mmu.c
@@ -31,7 +31,7 @@ void soc_mmu_init(void)
* Need to use secure mem attribute, as firmware is running in ARM TZ
* region.
*/
- mmu_config_range((void *)_ttb, _ttb_size, secure_mem);
+ mmu_config_range((void *)_ttb, REGION_SIZE(ttb), secure_mem);
mmu_config_range((void *)_dram, sdram_size_mb() * MiB, secure_mem);
/* IO space has the MSB set and is divided into 4 sub-regions:
* * NCB
diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c
index 7b9d524198..a512dffa00 100644
--- a/src/soc/cavium/common/bootblock.c
+++ b/src/soc/cavium/common/bootblock.c
@@ -42,7 +42,7 @@ void bootblock_main(const uint64_t reg_x0,
base_timestamp = timestamp_get();
/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
- if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
+ if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0)
timestamp_init(base_timestamp);
bootblock_soc_early_init();
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index 91c591e345..ac4a74070c 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -54,9 +54,9 @@ static void bootblock_mmu_init(void)
dram_base += null_guard_size;
dram_size -= null_guard_size;
}
- assert(!identity_map((uint32_t)_sram, _sram_size,
+ assert(!identity_map((uint32_t)_sram, REGION_SIZE(sram),
C0_ENTRYLO_COHERENCY_WB));
assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
- assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size,
- C0_ENTRYLO_COHERENCY_UC));
+ assert(!identity_map((uint32_t)_soc_registers,
+ REGION_SIZE(soc_registers), C0_ENTRYLO_COHERENCY_UC));
}
diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h
index 79c3ea022b..7fa847fd1d 100644
--- a/src/soc/mediatek/common/include/soc/mmu_operations.h
+++ b/src/soc/mediatek/common/include/soc/mmu_operations.h
@@ -17,6 +17,7 @@
#define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__
#include <arch/mmu.h>
+#include <symbols.h>
enum {
DEV_MEM = MA_DEV | MA_S | MA_RW,
@@ -26,9 +27,7 @@ enum {
NONSECURE_UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,
};
-extern unsigned char _sram_l2c[];
-extern unsigned char _esram_l2c[];
-#define _sram_l2c_size (_esram_l2c - _sram_l2c)
+DECLARE_REGION(sram_l2c)
void mtk_soc_after_dram(void);
void mtk_soc_disable_l2c_sram(void);
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
index 44670702de..7292487bed 100644
--- a/src/soc/mediatek/common/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -32,13 +32,13 @@ void mtk_mmu_init(void)
mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM);
/* SRAM is cached */
- mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM);
+ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM);
/* L2C SRAM is cached */
- mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM);
+ mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), SECURE_CACHED_MEM);
/* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
- mmu_config_range(_dma_coherent, _dma_coherent_size,
+ mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent),
SECURE_UNCACHED_MEM);
mmu_enable();
@@ -56,7 +56,7 @@ void mtk_mmu_disable_l2c_sram(void)
{
/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
/* TODO: Implement true unmapping, and also use it for the zero-page! */
- mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
+ mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), DEV_MEM);
/* Careful: changing cache geometry while it's active is a bad idea! */
mmu_disable();
diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c
index 0fe9bb4e57..d63b69c174 100644
--- a/src/soc/mediatek/mt8173/flash_controller.c
+++ b/src/soc/mediatek/mt8173/flash_controller.c
@@ -171,10 +171,10 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len,
if (ENV_BOOTBLOCK || ENV_VERSTAGE) {
dma_buf = (uintptr_t)_dma_coherent;
- dma_buf_len = _dma_coherent_size;
+ dma_buf_len = REGION_SIZE(dma_coherent);
} else {
dma_buf = (uintptr_t)_dram_dma;
- dma_buf_len = _dram_dma_size;
+ dma_buf_len = REGION_SIZE(dram_dma);
}
while (len - done >= SFLASH_DMA_ALIGN) {
diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h
index 8e2d0a4fb3..85cfd789ff 100644
--- a/src/soc/mediatek/mt8173/include/soc/symbols.h
+++ b/src/soc/mediatek/mt8173/include/soc/symbols.h
@@ -16,8 +16,6 @@
#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
-extern unsigned char _dram_dma[];
-extern unsigned char _edram_dma[];
-#define _dram_dma_size (_edram_dma - _dram_dma)
+DECLARE_REGION(dram_dma)
#endif
diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c
index 443bc6eb4d..c80226477a 100644
--- a/src/soc/mediatek/mt8173/mmu_operations.c
+++ b/src/soc/mediatek/mt8173/mmu_operations.c
@@ -23,7 +23,8 @@
void mtk_soc_after_dram(void)
{
- mmu_config_range(_dram_dma, _dram_dma_size, NONSECURE_UNCACHED_MEM);
+ mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
+ NONSECURE_UNCACHED_MEM);
mtk_mmu_disable_l2c_sram();
}
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c
index d99f1a719e..2495351f6c 100644
--- a/src/soc/nvidia/tegra124/verstage.c
+++ b/src/soc/nvidia/tegra124/verstage.c
@@ -30,7 +30,8 @@ static void enable_cache(void)
/* Whole space is uncached. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB,
+ DIV_ROUND_UP(REGION_SIZE(sram), MiB),
DCACHE_WRITEBACK);
mmu_disable_range(0, 1);
dcache_mmu_enable();
diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c
index de7ae2f487..9cee6b2f29 100644
--- a/src/soc/nvidia/tegra210/mmu_operations.c
+++ b/src/soc/nvidia/tegra210/mmu_operations.c
@@ -45,7 +45,7 @@ static void tegra210_mmu_config(void)
mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem);
/* SRAM */
- mmu_config_range(_sram, _sram_size, cachedmem);
+ mmu_config_range(_sram, REGION_SIZE(sram), cachedmem);
/* Add TZ carveout. */
carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
@@ -89,8 +89,8 @@ void tegra210_mmu_init(void)
*
*/
carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
- assert((uintptr_t)_ttb + _ttb_size == (tz_base_mib + tz_size_mib) * MiB
- && _ttb_size <= tz_size_mib * MiB);
+ assert((uintptr_t)_ttb + REGION_SIZE(ttb) == (tz_base_mib + tz_size_mib)
+ * MiB && REGION_SIZE(ttb) <= tz_size_mib * MiB);
mmu_enable();
}
diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h
index 163b54dc51..1c14c03d01 100644
--- a/src/soc/qualcomm/sdm845/include/soc/symbols.h
+++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h
@@ -16,18 +16,11 @@
#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_
#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_
+#include <symbols.h>
#include <types.h>
-extern u8 _ssram[];
-extern u8 _essram[];
-#define _ssram_size (_essram - _ssram)
-
-extern u8 _bsram[];
-extern u8 _ebsram[];
-#define _bsram_size (_ebsram - _bsram)
-
-extern u8 _dram_reserved[];
-extern u8 _edram_reserved[];
-#define _dram_reserved_size (_edram_reserved - _dram_reserved)
+DECLARE_REGION(ssram)
+DECLARE_REGION(bsram)
+DECLARE_REGION(dram_reserved)
#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_
diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c
index 52e7733fa5..ef6c058ab3 100644
--- a/src/soc/qualcomm/sdm845/mmu.c
+++ b/src/soc/qualcomm/sdm845/mmu.c
@@ -28,9 +28,9 @@ void sdm845_mmu_init(void)
mmu_init();
mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
- mmu_config_range((void *)_ssram, _ssram_size, CACHED_RAM);
- mmu_config_range((void *)_bsram, _bsram_size, CACHED_RAM);
- mmu_config_range((void *)_dma_coherent, _dma_coherent_size,
+ mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
+ mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
+ mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
UNCACHED_RAM);
mmu_enable();
diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c
index 56e2c8456a..e4eac96276 100644
--- a/src/soc/qualcomm/sdm845/soc.c
+++ b/src/soc/qualcomm/sdm845/soc.c
@@ -23,7 +23,7 @@ static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB);
reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB,
- _dram_reserved_size / KiB);
+ REGION_SIZE(dram_reserved) / KiB);
}
static void soc_init(struct device *dev)
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 7308241e17..5ccfebd583 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -33,7 +33,7 @@ void bootblock_soc_init(void)
/* SRAM is tightly wedged between registers, need to use subtables. Map
* write-through as equivalent for non-cacheable without XN on A17. */
mmu_config_range_kb((uintptr_t)_sram/KiB,
- _sram_size/KiB, DCACHE_WRITETHROUGH);
+ REGION_SIZE(sram)/KiB, DCACHE_WRITETHROUGH);
dcache_mmu_enable();
rkclk_configure_crypto(148500*KHz);
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index c0a2ed002e..ad679e59b9 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -34,7 +34,7 @@ static void soc_init(struct device *dev)
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
if (display_init_required())
rk_display_init(dev, (uintptr_t)_framebuffer,
- _framebuffer_size);
+ REGION_SIZE(framebuffer));
else
printk(BIOS_INFO, "Skipping display init.\n");
}
diff --git a/src/soc/rockchip/rk3399/decompressor.c b/src/soc/rockchip/rk3399/decompressor.c
index f4ca5d111f..a17900de50 100644
--- a/src/soc/rockchip/rk3399/decompressor.c
+++ b/src/soc/rockchip/rk3399/decompressor.c
@@ -30,7 +30,7 @@ void decompressor_soc_init(void)
*/
mmu_config_range((void *)0, (uintptr_t)4 * GiB, DEV_MEM);
- mmu_config_range(_sram, _sram_size, SECURE_MEM);
+ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_MEM);
mmu_enable();
}
diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h
index f1487d0cb6..a40a7c48d3 100644
--- a/src/soc/rockchip/rk3399/include/soc/symbols.h
+++ b/src/soc/rockchip/rk3399/include/soc/symbols.h
@@ -16,12 +16,9 @@
#ifndef __SOC_SYMBOLS_H__
#define __SOC_SYMBOLS_H__
-extern unsigned char _bl31_sram[];
-extern unsigned char _ebl31_sram[];
-#define _bl31_sram_size (_ebl31_sram - _bl31_sram)
+#include <symbols.h>
-extern unsigned char _pmu_sram[];
-extern unsigned char _epmu_sram[];
-#define _pmu_sram_size (_epmu_sram - _pmu_sram)
+DECLARE_REGION(bl31_sram)
+DECLARE_REGION(pmu_sram)
#endif
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 8960c9e202..6e5e1a7f96 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -30,8 +30,10 @@
void bootmem_platform_add_ranges(void)
{
- bootmem_add_range((uintptr_t)_pmu_sram, _pmu_sram_size, BM_MEM_BL31);
- bootmem_add_range((uintptr_t)_bl31_sram, _bl31_sram_size, BM_MEM_BL31);
+ bootmem_add_range((uintptr_t)_pmu_sram, REGION_SIZE(pmu_sram),
+ BM_MEM_BL31);
+ bootmem_add_range((uintptr_t)_bl31_sram, REGION_SIZE(bl31_sram),
+ BM_MEM_BL31);
}
static void soc_read_resources(struct device *dev)
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index 0687d47a5d..e7ceedb15c 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -88,7 +88,7 @@ static int sdmmc_cbfs_open(void)
* figuring out the true image size from in here. Since this is mainly a
* developer/debug boot mode, those shortcomings should be bearable.
*/
- const u32 count = _cbfs_cache_size / 512;
+ const u32 count = REGION_SIZE(cbfs_cache) / 512;
static int first_run = 1;
int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
*irom_sdmmc_read_blocks_ptr;
@@ -131,7 +131,7 @@ const struct region_device *boot_device_ro(void)
void boot_device_init(void)
{
mem_region_device_ro_init(&alternate_rdev, _cbfs_cache,
- _cbfs_cache_size);
+ REGION_SIZE(cbfs_cache));
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c
index 9406abb302..ae67407c6d 100644
--- a/src/soc/samsung/exynos5250/spi.c
+++ b/src/soc/samsung/exynos5250/spi.c
@@ -179,7 +179,7 @@ void exynos_init_spi_boot_device(void)
{
boot_slave_regs = (void *)EXYNOS5_SPI1_BASE;
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+ mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache));
}
const struct region_device *exynos_spi_boot_device(void)
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c
index 183c3710ef..98674ba8dc 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.c
@@ -92,7 +92,7 @@ static int sdmmc_cbfs_open(void)
* figuring out the true image size from in here. Since this is mainly a
* developer/debug boot mode, those shortcomings should be bearable.
*/
- const u32 count = _cbfs_cache_size / 512;
+ const u32 count = REGION_SIZE(cbfs_cache) / 512;
static int first_run = 1;
int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
*irom_sdmmc_read_blocks_ptr;
@@ -138,7 +138,7 @@ const struct region_device *boot_device_ro(void)
void boot_device_init(void)
{
mem_region_device_ro_init(&alternate_rdev, _cbfs_cache,
- _cbfs_cache_size);
+ REGION_SIZE(cbfs_cache));
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 2023b10130..3ce9457e78 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -287,7 +287,7 @@ void exynos_init_spi_boot_device(void)
{
boot_slave = &exynos_spi_slaves[1];
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+ mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache));
}
const struct region_device *exynos_spi_boot_device(void)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 18:41:04 +0000