diff options
Diffstat (limited to 'src/soc')
31 files changed, 283 insertions, 290 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bc1a80575d..dcf1b1a0af 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -93,6 +93,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ce89f133ee..cf3e8395de 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2018 Intel Corp. * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -25,6 +25,7 @@ #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> +#include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -87,8 +88,6 @@ static void enable_pmcbar(void) void bootblock_soc_early_init(void) { - uint32_t reg; - enable_pmcbar(); /* Clear global reset promotion bit */ @@ -110,10 +109,8 @@ void bootblock_soc_early_init(void) /* Initialize GPE for use as interrupt status */ pmc_gpe_init(); - /* Stop TCO timer */ - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HLT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); + /* Program TCO Timer Halt */ + tco_configure(); /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 361b041f5c..b03d5e65c2 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -21,6 +21,7 @@ #include <intelblocks/pmclib.h> #include <soc/pm.h> #include <soc/pci_devs.h> +#include <soc/smbus.h> #include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) @@ -80,7 +81,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco_sts & TCO_TIMEOUT) + ps->tco1_sts & TCO_TIMEOUT) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index b1cf3da88a..8e2986d8b7 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -29,6 +29,9 @@ #define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 +#define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60) +#define TCO_BASE_SIZE 0x20 + /* CST Range (R/W) IO port block size */ #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 /* ACPI PMIO Offset to C-state register*/ diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 4af8f2c23e..264704c755 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -40,5 +40,6 @@ #define PID_TUNIT 0x52 #define PID_PSF3 0xC6 +#define PID_DMI 0x00 /* Reserved */ #endif /* SOC_INTEL_APL_PCR_H */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c4f1d1b39c..61c97cebb5 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -131,10 +131,6 @@ #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c -#define TCO_STS 0x64 -#define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -#define TCO_TMR_HLT (1 << 11) #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 @@ -240,7 +236,8 @@ struct chipset_power_state { uint32_t pm1_cnt; uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t gpe0_en[GPE0_REG_MAX]; - uint32_t tco_sts; + uint16_t tco1_sts; + uint16_t tco2_sts; uint32_t prsts; uint32_t gen_pmcon1; uint32_t gen_pmcon2; diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h new file mode 100644 index 0000000000..4b252d61a9 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SMBUS_H_ +#define _SOC_APOLLOLAKE_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) + +#endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c36d84d8de..812a16a23a 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -28,11 +28,13 @@ #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <intelblocks/tco.h> #include <rules.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/smbus.h> #include <timer.h> #include <security/vboot/vbnv.h> #include "chip.h" @@ -133,15 +135,6 @@ const char *const *soc_std_gpe_sts_array(size_t *a) return gpe_sts_bits; } -uint32_t soc_reset_tco_status(void) -{ - uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - - outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS); - return tco_sts & tco_en; -} - void soc_clear_pm_registers(uintptr_t pmc_bar) { uint32_t gen_pmcon1; @@ -173,14 +166,18 @@ void soc_fill_power_state(struct chipset_power_state *ps) { uintptr_t pmc_bar0 = read_pmc_mmio_bar(); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); - printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n", - ps->prsts, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x\n", + ps->prsts); + printk(BIOS_DEBUG, "tco_sts: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); printk(BIOS_DEBUG, "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 73e159ab09..f45e177c0a 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +24,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/smbus.h> +#include <intelblocks/tco.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -52,8 +53,6 @@ #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_TCOBASE 0x2778 -#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 @@ -141,35 +140,6 @@ static void soc_config_acpibase(void) } } -static void soc_config_tco(void) -{ - uint32_t reg32; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~TCO_BASE_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - tcobase = TCO_BASE_ADDRESS; - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); - - /* Program TCO timer halt */ - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - static int pch_check_decode_enable(void) { uint32_t dmi_control; @@ -216,7 +186,7 @@ void pch_early_init(void) soc_config_acpibase(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); + tco_configure(); /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index b3c07b1154..03ff616a60 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/tco.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> @@ -55,17 +56,11 @@ static void pch_finalize(void) { struct device *dev; uint32_t reg32; - uint16_t tcobase, tcocnt; uint8_t *pmcbase; config_t *config; uint8_t reg8; - /* TCO Lock down */ - tcobase = smbus_tco_regs(); - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_LOCK; - outw(tcocnt, tcobase + TCO1_CNT); - + tco_lockdown(); /* * Disable ACPI PM timer based on dt policy * diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 9f1cf34862..e3d93a2a54 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -4,7 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,11 +19,6 @@ #ifndef _SOC_CANNONLAKE_SMBUS_H_ #define _SOC_CANNONLAKE_SMBUS_H_ -/* PCI registers */ -#define TCOBASE 0x50 /* TCO base address. */ -#define TCOCTL 0x54 -#define TCO_BASE_EN (1 << 8) /* TCO base enable. */ - /* IO and MMIO registers under primary BAR */ /* Set address for PCH as SMBus slave role */ #define SMB_RCV_SLVA 0x09 @@ -32,10 +27,10 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 951d8863ac..b57102df42 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <intelblocks/tco.h> #include <halt.h> #include <rules.h> #include <stdlib.h> @@ -154,38 +155,6 @@ uint8_t *pmc_mmio_regs(void) return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; } -uint16_t smbus_tco_regs(void) -{ - uint16_t reg16; - - reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - - return ALIGN_DOWN(reg16, 0x20); -} - -uint32_t soc_reset_tco_status(void) -{ - u16 tco1_sts; - u16 tco2_sts; - u16 tcobase; - - tcobase = smbus_tco_regs(); - - /* TCO Status 2 register */ - tco2_sts = inw(tcobase + TCO2_STS); - tco2_sts |= TCO2_STS_SECOND_TO; - outw(tco2_sts, tcobase + TCO2_STS); - - /* TCO Status 1 register */ - tco1_sts = inw(tcobase + TCO1_STS); - - /* Clear SECOND_TO_STS bit */ - if (tco2_sts & TCO2_STS_SECOND_TO) - outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); - - return (tco2_sts << 16) | tco1_sts; -} - uintptr_t soc_read_pmc_base(void) { return (uintptr_t)pmc_mmio_regs(); diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c index 72361ff83a..99a93accbe 100644 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ b/src/soc/intel/cannonlake/romstage/power_state.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> #include <intelblocks/pmclib.h> +#include <intelblocks/tco.h> #include <string.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -66,13 +67,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, void soc_fill_power_state(struct chipset_power_state *ps) { - uint16_t tcobase; uint8_t *pmc; - tcobase = smbus_tco_regs(); - - ps->tco1_sts = inw(tcobase + TCO1_STS); - ps->tco2_sts = inw(tcobase + TCO2_STS); + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index e1c29be1ad..82eb2ae4c4 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -93,13 +93,6 @@ uint32_t pmc_clear_tco_status(void); */ const char *const *soc_tco_sts_array(size_t *a); -/* - * Resets the tco status registers. This function clears the tco_sts register - * and returns the sts and enable bits set. - */ -uint32_t soc_reset_tco_status(void); - - /* GPE */ /* diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h new file mode 100644 index 0000000000..86fa33b61a --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_TCO_H +#define SOC_INTEL_COMMON_BLOCK_TCO_H + +#include <stdint.h> + +/* + * Enable TCO BAR using SMBUS TCO base to access TCO related register + * also disable the timer. + */ +void tco_configure(void); +/* Lockdown TCO registers before booting to OS */ +void tco_lockdown(void); +/* + * Resets the tco status registers. This function clears the tco_sts register + * and returns the status bits set. + */ +uint32_t tco_reset_status(void); +uint16_t tco_read_reg(uint16_t tco_reg); +void tco_write_reg(uint16_t tco_reg, uint16_t value); + +#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 4a1da9ecb9..a4696805a1 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -20,6 +20,7 @@ #include <halt.h> #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> +#include <intelblocks/tco.h> #include <soc/pm.h> #include <string.h> #include <timer.h> @@ -260,7 +261,7 @@ static uint32_t print_tco_status(uint32_t tco_sts) uint32_t pmc_clear_tco_status(void) { - return print_tco_status(soc_reset_tco_status()); + return print_tco_status(tco_reset_status()); } /* GPE */ diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index 4514383364..fe940ccab0 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -2,3 +2,14 @@ config SOC_INTEL_COMMON_BLOCK_SMBUS bool help Intel Processor common SMBus support + +config SOC_INTEL_COMMON_BLOCK_TCO + bool + help + Intel Processor common TCO support + +config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS + bool + depends on SOC_INTEL_COMMON_BLOCK_TCO + help + Select this config to enable TCO BAR through SMBUS diff --git a/src/soc/intel/common/block/smbus/Makefile.inc b/src/soc/intel/common/block/smbus/Makefile.inc index 1a10fd9735..309ad9a3d8 100644 --- a/src/soc/intel/common/block/smbus/Makefile.inc +++ b/src/soc/intel/common/block/smbus/Makefile.inc @@ -1,8 +1,15 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c + +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c new file mode 100644 index 0000000000..14589450d2 --- /dev/null +++ b/src/soc/intel/common/block/smbus/tco.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <intelblocks/pcr.h> +#include <intelblocks/tco.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <soc/smbus.h> + +#define PCR_DMI_TCOBASE 0x2778 +/* Enable TCO I/O range decode. */ +#define TCOEN (1 << 1) + +/* SMBUS TCO base address. */ +#define TCOBASE 0x50 +#define TCOCTL 0x54 +#define TCO_BASE_EN (1 << 8) + +/* Get base address of TCO I/O registers. */ +static uint16_t tco_get_bar(void) +{ + return TCO_BASE_ADDRESS; +} + +uint16_t tco_read_reg(uint16_t tco_reg) +{ + uint16_t tcobase; + + tcobase = tco_get_bar(); + + return inw(tcobase + tco_reg); +} + +void tco_write_reg(uint16_t tco_reg, uint16_t value) +{ + uint16_t tcobase; + + tcobase = tco_get_bar(); + + outw(value, tcobase + tco_reg); +} + +void tco_lockdown(void) +{ + uint16_t tcocnt; + + /* TCO Lock down */ + tcocnt = tco_read_reg(TCO1_CNT); + tcocnt |= TCO_LOCK; + tco_write_reg(TCO1_CNT, tcocnt); +} + +uint32_t tco_reset_status(void) +{ + uint16_t tco1_sts; + uint16_t tco2_sts; + + /* TCO Status 2 register */ + tco2_sts = tco_read_reg(TCO2_STS); + tco2_sts |= TCO_STS_SECOND_TO; + tco_write_reg(TCO2_STS, tco2_sts); + + /* TCO Status 1 register */ + tco1_sts = tco_read_reg(TCO1_STS); + + return (tco2_sts << 16) | tco1_sts; +} + +/* Stop TCO timer */ +static void tco_timer_disable(void) +{ + uint16_t tcocnt; + + /* Program TCO timer halt */ + tcocnt = tco_read_reg(TCO1_CNT); + tcocnt |= TCO_TMR_HLT; + tco_write_reg(TCO1_CNT, tcocnt); +} + +/* Enable TCO BAR using SMBUS TCO base to access TCO related register */ +static void tco_enable_bar(void) +{ + uint32_t reg32; + uint16_t tcobase; +#if defined(__SIMPLE_DEVICE__) + int devfn = PCH_DEVFN_SMBUS; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); +#else + struct device *dev; + dev = PCH_DEV_SMBUS; +#endif + + /* Disable TCO in SMBUS Device first before changing Base Address */ + reg32 = pci_read_config32(dev, TCOCTL); + reg32 &= ~TCO_BASE_EN; + pci_write_config32(dev, TCOCTL, reg32); + + /* Program TCO Base */ + tcobase = tco_get_bar(); + pci_write_config32(dev, TCOBASE, tcobase); + + /* Enable TCO in SMBUS */ + pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); + + /* + * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] + */ + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); +} + +/* + * Enable TCO BAR using SMBUS TCO base to access TCO related register + * also disable the timer. + */ +void tco_configure(void) +{ + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) + tco_enable_bar(); + + tco_timer_disable(); +} diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 538028d76a..16f31b6756 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -31,6 +31,7 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <soc/iomap.h> +#include <soc/smbus.h> #include <spi-generic.h> #include <stdint.h> #include <stdlib.h> diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index f4f3ad004f..a832742f5e 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -37,6 +37,8 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_TCO + select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 28d669aa2c..2afb358726 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -23,6 +23,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/smbus.h> +#include <intelblocks/tco.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -49,9 +50,6 @@ #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_TCOBASE 0x2778 -/* Enable TCO I/O range decode. */ -#define TCOEN (1 << 1) #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 @@ -119,35 +117,6 @@ static void soc_config_acpibase(void) } } -static void soc_config_tco(void) -{ - uint32_t reg32; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~TCO_BASE_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - tcobase = TCO_BASE_ADDRESS; - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); - - /* Program TCO timer halt */ - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - static int pch_check_decode_enable(void) { uint32_t dmi_control; @@ -194,7 +163,7 @@ void pch_early_init(void) soc_config_acpibase(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); + tco_configure(); /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index fb78350709..a9c9ea12c3 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/tco.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> @@ -54,16 +55,12 @@ static void pch_finalize(void) { struct device *dev; uint32_t reg32; - uint16_t tcobase, tcocnt; uint8_t *pmcbase; config_t *config; uint8_t reg8; /* TCO Lock down */ - tcobase = smbus_tco_regs(); - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_LOCK; - outw(tcocnt, tcobase + TCO1_CNT); + tco_lockdown(); /* * Disable ACPI PM timer based on dt policy diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 64c3eb3f3a..f4f5b11288 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -16,11 +16,6 @@ #ifndef _SOC_ICELAKE_SMBUS_H_ #define _SOC_ICELAKE_SMBUS_H_ -/* PCI registers */ -#define TCOBASE 0x50 /* TCO base address. */ -#define TCOCTL 0x54 -#define TCO_BASE_EN (1 << 8) /* TCO base enable. */ - /* IO and MMIO registers under primary BAR */ /* Set address for PCH as SMBus slave role */ #define SMB_RCV_SLVA 0x09 @@ -29,10 +24,10 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index c020bf61d6..abd52c4ff0 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <intelblocks/tco.h> #include <halt.h> #include <rules.h> #include <stdlib.h> @@ -153,38 +154,6 @@ uint8_t *pmc_mmio_regs(void) return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; } -uint16_t smbus_tco_regs(void) -{ - uint16_t reg16; - - reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - - return ALIGN_DOWN(reg16, 0x20); -} - -uint32_t soc_reset_tco_status(void) -{ - u16 tco1_sts; - u16 tco2_sts; - u16 tcobase; - - tcobase = smbus_tco_regs(); - - /* TCO Status 2 register */ - tco2_sts = inw(tcobase + TCO2_STS); - tco2_sts |= TCO2_STS_SECOND_TO; - outw(tco2_sts, tcobase + TCO2_STS); - - /* TCO Status 1 register */ - tco1_sts = inw(tcobase + TCO1_STS); - - /* Clear SECOND_TO_STS bit */ - if (tco2_sts & TCO2_STS_SECOND_TO) - outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); - - return (tco2_sts << 16) | tco1_sts; -} - uintptr_t soc_read_pmc_base(void) { return (uintptr_t)pmc_mmio_regs(); diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c index 17ed36a9d9..3f1a211c6c 100644 --- a/src/soc/intel/icelake/romstage/power_state.c +++ b/src/soc/intel/icelake/romstage/power_state.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <device/device.h> #include <intelblocks/pmclib.h> +#include <intelblocks/tco.h> #include <string.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -65,13 +66,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, void soc_fill_power_state(struct chipset_power_state *ps) { - uint16_t tcobase; uint8_t *pmc; - tcobase = smbus_tco_regs(); - - ps->tco1_sts = inw(tcobase + TCO1_STS); - ps->tco2_sts = inw(tcobase + TCO2_STS); + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 26ea56a93a..6403ed3ee7 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,8 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,6 +26,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/smbus.h> +#include <intelblocks/tco.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/p2sb.h> @@ -43,7 +43,6 @@ #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_TCOBASE 0x2778 void bootblock_pch_early_init(void) { @@ -112,37 +111,6 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); } -static void soc_config_tco(void) -{ - uint32_t reg32 = 0; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~TCO_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - * to [SMBUS PCI offset 50h[15:5], 1]. - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1)); - - /* Program TCO timer halt */ - tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - tcobase &= ~0x1f; - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - static int pch_check_decode_enable(void) { uint32_t dmi_control; @@ -196,7 +164,7 @@ void pch_early_init(void) soc_config_pwrmbase(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); + tco_configure(); /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1fab92e2b0..de790fa461 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -373,7 +373,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO2_STS_SECOND_TO) + ps->tco2_sts & TCO_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 47e3941531..f622edbde9 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -183,9 +183,6 @@ int acpi_sci_irq(void); /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -/* Get base address of TCO I/O registers. */ -uint16_t smbus_tco_regs(void); - /* Set the DISB after DRAM init */ void pmc_set_disb(void); diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index aeaf1d9ea2..aad57aabb6 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -4,7 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,20 +22,14 @@ /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_RCV_SLVA 0x09 -/* SMBUS TCO base address. */ -#define TCOBASE 0x50 -#define TCOCTL 0x54 -#define TCO_EN (1 << 8) - /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_BOOT 0x04 +#define TCO_STS_SECOND_TO 0x02 #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2e1d1713e1..335df53ddc 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -28,6 +28,7 @@ #include <intelblocks/pmclib.h> #include <halt.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/tco.h> #include <rules.h> #include <stdlib.h> #include <soc/gpe.h> @@ -168,40 +169,6 @@ uint8_t *pmc_mmio_regs(void) return (void *)(uintptr_t) reg32; } -uint16_t smbus_tco_regs(void) -{ - uint16_t reg16; - - reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - - reg16 &= ~0x1f; - - return reg16; -} - -uint32_t soc_reset_tco_status(void) -{ - u16 tco1_sts; - u16 tco2_sts; - u16 tcobase; - - tcobase = smbus_tco_regs(); - - /* TCO Status 2 register */ - tco2_sts = inw(tcobase + TCO2_STS); - tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT); - outw(tco2_sts, tcobase + TCO2_STS); - - /* TCO Status 1 register */ - tco1_sts = inw(tcobase + TCO1_STS); - - /* Clear SECOND_TO_STS bit */ - if (tco2_sts & TCO2_STS_SECOND_TO) - outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); - - return (tco2_sts << 16) | tco1_sts; -} - uintptr_t soc_read_pmc_base(void) { return (uintptr_t) (pmc_mmio_regs()); @@ -285,13 +252,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, void soc_fill_power_state(struct chipset_power_state *ps) { - uint16_t tcobase; uint8_t *pmc; - tcobase = smbus_tco_regs(); - - ps->tco1_sts = inw(tcobase + TCO1_STS); - ps->tco2_sts = inw(tcobase + TCO2_STS); + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); |