diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/sc7180/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/aop_load_reset.c | 43 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/aop.h | 21 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 9 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/symbols.h | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/mmu.c | 5 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/soc.c | 7 |
7 files changed, 85 insertions, 2 deletions
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index e1d0492085..8a76a03c9c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000000..8d22d62056 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/aop.h> +#include <soc/clock.h> + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000000..5573163a5b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 3f43419d14..732311953e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,16 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) @@ -52,6 +60,7 @@ SECTIONS DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x300000, 0x1000) BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f379bb98e3..d2a53fbf92 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -25,5 +25,6 @@ DECLARE_REGION(dram_soc) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 231b06f819..2eb8c86994 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -32,3 +32,8 @@ void sc7180_mmu_init(void) mmu_enable(); } + +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 7003b39a75..fbcfc6ed8d 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,18 +18,21 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> +#include <soc/aop.h> static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); - reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, + REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); } static void soc_init(struct device *dev) { - + aop_fw_load_reset(); } static struct device_operations soc_ops = { |