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-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/lpc.h4
-rw-r--r--src/soc/intel/fsp_broadwell_de/romstage/romstage.c7
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
index 2c02ebdf47..0408f7f640 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
@@ -21,6 +21,8 @@
#define REVID 0x08
#define PIRQ_RCR1 0x60
#define PIRQ_RCR2 0x68
+#define LPC_IO_DEC 0x80
+#define LPC_EN 0x82
#define GEN_PMCON_1 0xA0
#define GEN_PMCON_2 0xA2
#define GEN_PMCON_3 0xA4
@@ -83,4 +85,4 @@
#define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70
-#endif /* _SOC_LPC_H_ */ \ No newline at end of file
+#endif /* _SOC_LPC_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 91c2532af0..309a672710 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -48,6 +48,13 @@ static void init_rtc(void)
void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
{
post_code(0x40);
+ if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) {
+ /* Enable decoding of I/O locations for Super I/O devices */
+ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
+ LPC_IO_DEC, 0x0010);
+ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
+ LPC_EN, 0x340f);
+ }
console_init();
init_rtc();