diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra124/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/bootblock.c | 81 |
2 files changed, 82 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 9ed7669aea..8966168a78 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -28,7 +28,10 @@ verstage-y += spi.c verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c +verstage-y += clock.c +verstage-y += i2c.c romstage-y += cbfs.c romstage-y += cbmem.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index aec914532e..22e7ba8557 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,6 +18,7 @@ */ #include <assert.h> +#include <arch/cache.h> #include <arch/exception.h> #include <bootblock_common.h> #include <cbfs.h> @@ -27,6 +28,78 @@ #include "pinmux.h" #include "power.h" #include "verstage.h" +#include <soc/addressmap.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void setup_pinmux(void) +{ + // Write protect. + gpio_input_pullup(GPIO(R1)); + // Recovery mode. + gpio_input_pullup(GPIO(Q7)); + // Lid switch. + gpio_input_pullup(GPIO(R4)); + // Power switch. + gpio_input_pullup(GPIO(Q0)); + // Developer mode. + gpio_input_pullup(GPIO(Q6)); + // EC in RW. + gpio_input_pullup(GPIO(U4)); + + // route PU4/5 to GMI to remove conflict w/PWM1/2. + pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); + pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); + + // SOC and TPM reset GPIO, active low. + gpio_output(GPIO(I5), 1); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + // switch unused pin to GPIO + gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); +} + +static void configure_ec_spi_bus(void) +{ + clock_configure_source(sbc1, CLK_M, 3000); +} + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); + + i2c_init(2); +} void main(void) { @@ -70,9 +143,13 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); - if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) + if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) { + clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); + setup_pinmux(); + configure_ec_spi_bus(); + configure_tpm_i2c_bus(); entry = (void *)verstage_vboot_main; - else + } else entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); ASSERT(entry); |