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-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 1f26f1e146..ab7c765043 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -162,6 +162,8 @@ struct soc_intel_cannonlake_config {
uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+ /* Enable/Disable HotPlug support for Root Port */
+ uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a198f1bfec..17a014b97e 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -188,6 +188,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcClkReq));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
+ memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
+ sizeof(config->PcieRpHotPlug));
/* eMMC and SD */
dev = dev_find_slot(0, PCH_DEVFN_EMMC);