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-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 6e492bb73a..77bad8f627 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -50,7 +50,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->PcieRpEnableMask = mask;
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->EnableC6Dram = config->enable_c6dram;
+#if CONFIG(SOC_INTEL_COMETLAKE)
+ m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+#else
m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+#endif
/*
* PcdDebugInterfaceFlags
* This config will allow coreboot to pass information to the FSP