12 files changed, 19 insertions, 45 deletions

diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c
index 9b9c426733..fe127aab91 100644
--- a/src/soc/dmp/vortex86ex/hard_reset.c
+++ b/src/soc/dmp/vortex86ex/hard_reset.c
@@ -16,6 +16,6 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 }
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
index fc581df98e..c0e9105abf 100644
--- a/src/soc/imgtec/pistachio/reset.c
+++ b/src/soc/imgtec/pistachio/reset.c
@@ -20,7 +20,7 @@
 #define PISTACHIO_WD_ADDR		0xB8102100
 #define PISTACHIO_WD_SW_RST_OFFSET	0x0000
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Generate system reset */
 	write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 56273cc03e..15e78fe203 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -23,13 +23,13 @@
 
 #define CSE_WAIT_MAX_MS							1000
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	global_reset_enable(1);
-	hard_reset();
+	do_hard_reset();
 }
 
-void reset_prepare(void)
+void soc_reset_prepare(enum reset_type reset_type)
 {
 	struct stopwatch sw;
 
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
index fd38f61255..e38a2e6ec8 100644
--- a/src/soc/intel/baytrail/reset.c
+++ b/src/soc/intel/baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index e4d01c2790..ad90dcd880 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -28,12 +28,12 @@
  * with ETR[20] set.
  */
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index e9be1855b0..06a534ce99 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,39 +25,16 @@
 #define RST_CPU			(1 << 2)
 #define SYS_RST			(1 << 1)
 
-#ifdef __ROMCC__
-#define WEAK
-#else
-#define WEAK __attribute__((weak))
-#endif
-
-void WEAK reset_prepare(void) { /* do nothing */ }
-
 #if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
-void hard_reset(void)
+void do_hard_reset(void)
 {
-	reset_prepare();
 	/* S0->S5->S0 trip. */
 	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
-	while (1)
-		hlt();
 }
 #endif
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
-	reset_prepare();
 	/* PMC_PLTRST# asserted. */
 	outb(RST_CPU | SYS_RST, RST_CNT);
-	while (1)
-		hlt();
-}
-
-void cpu_reset(void)
-{
-	reset_prepare();
-	/* Sends INIT# to CPU */
-	outb(RST_CPU, RST_CNT);
-	while (1)
-		hlt();
 }
diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c
index fd38f61255..e38a2e6ec8 100644
--- a/src/soc/intel/fsp_baytrail/reset.c
+++ b/src/soc/intel/fsp_baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
index 7e1c582749..78d74939e3 100644
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ b/src/soc/intel/fsp_broadwell_de/reset.c
@@ -23,7 +23,7 @@ void warm_reset(void)
     outb(0x06, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	warm_reset();
 }
diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c
index 2574565f75..91bcd690ca 100644
--- a/src/soc/intel/sch/reset.c
+++ b/src/soc/intel/sch/reset.c
@@ -17,12 +17,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x02, 0xcf9);
 	outb(0x06, 0xcf9);
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 69109145f2..dee98a4c1e 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -41,7 +41,7 @@ static void do_force_global_reset(void)
 	hard_reset();
 }
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	if (send_global_reset() != 0) {
 		/* If ME unable to reset platform then
diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c
index 93ffe09209..22f1c87ac5 100644
--- a/src/soc/mediatek/mt8173/wdt.c
+++ b/src/soc/mediatek/mt8173/wdt.c
@@ -57,10 +57,7 @@ int mtk_wdt_init(void)
 	return wdt_sta;
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
-
-	while (1)
-		;
 }
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index f27650dae6..de99a82321 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -39,7 +39,7 @@ void power_reset(void)
 	setbits_le32(&exynos_power->sw_reset, 1);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	power_reset();
 }